Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

SangGi Do

dblp:196/6125 · DBLP profile ↗
← Back
3ranked-venue papers
1as first author
0since 2021 · last 2020
0000-0003-0170-1354ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.722020
Compact Topology-Aware Bus Routing for Design Regularity · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization · DAC 2017
Electronic design automation › physical design › routing › VLSI routing
bus routing
0.412020
Compact Topology-Aware Bus Routing for Design Regularity · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › physical design
routing
0.412020
Compact Topology-Aware Bus Routing for Design Regularity · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › physical design › clock network synthesis
clock tree synthesis
0.312017
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization · DAC 2017
Electronic design automation › physical design › placement
timing-driven placement
0.312017
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization · DAC 2017
Electronic design automation › physical design › timing optimization
useful skew
0.312017
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization · DAC 2017
Electronic design automation › physical design
timing optimization
0.112017
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization · DAC 2017

Methods — techniques the papers use, named apart from their topics

topology-aware routing · 0.4maximum mean weight cycle · 0.3clock latency optimization · 0.3
YearPublicationVenuePosition
2020 Compact Topology-Aware Bus Routing for Design Regularity
abstract
In bus routing, if signal bits in a bus structure share a common routing topology, routability is increased by avoiding twisted patterns and variation immunity. The bus routing problem has become significantly important because of increasing complexity of bus structures for multichip-module, I/O pins, or on-chip memories in advanced technology. We present and evaluate a compact topology-aware bus routing method that can both compactly synthesize the routing topology of the bus and minimize design rule violations even in designs with high bus density and high track utilization. Our proposed method completed the bus routing in the runtime limit of the ICCAD-2018 contest and achieved 66% reduction in total cost compared with the winner of that contest.
SangGi Do, Sung-Yun Lee, Seokhyeong Kang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2019 Fence-Region-Aware Mixed-Height Standard Cell Legalization
abstract
We propose a fence-region-aware mixed-height standard cell legalization that can optimize the placement of standard cells that have more than a two row height in various shapes of the fence region. The algorithm consists of pre-legalization and mixed-height standard cell legalization steps to prioritize cell legalization; then a quality refinement step that uses simulated annealing reduces the displacement. Our proposed method achieved 63% improvement in the average quality score and 72% improvement in average runtime, compared to the winners of the ICCAD-2017 contest.
SangGi Do, Mingyu Woo, Seokhyeong Kang
ACM Great Lakes Symposium on VLSI1
2017 Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization
abstract
Incremental timing-driven placement (TDP) is one of the most crucial steps for timing closure in a physical design. The need for high-performance incremental TDP continues to grow, but prior studies have focused on optimizing only setup timing slacks, which can be easily stuck in local optima. In this paper, we present a useful skew methodology based on a maximum mean weight cycle (MMWC) approach in the incremental TDP. The proposed useful skew methodology finds an optimal clock latency for each flip-flop, and the clock latency is implemented by moving the flip-flops and/ or reassigning them to local clock buffers. With the proposed TDP method, we effectively reduce the early slack of ICCAD 2015 contest benchmarks, and achieve 124(%) and 78(%) of total quality score improvement compared to the 2015 contest winner, and early slack histogram compression (EHC) method, respectively. Moreover, with fewer iterations in the optimization, the runtime of our predictive useful skew method is an average of 7.4 times faster than an EHC method.
Seungwon Kim, SangGi Do, Seokhyeong Kang
DAC2