EDBT 2026 Demo / reviewers in the wild / expert
Kyungseon Cho
dblp:196/6292
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 46% Memory systems · 46% Energy-efficient computing · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA architecture |
0.6 | 1 | 2022 | STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Reconfigurable computing and FPGAs › dynamic reconfiguration
multicontext FPGA |
0.6 | 1 | 2022 | STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Memory systems
non-volatile memory |
0.6 | 1 | 2022 | STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Memory systems › non-volatile memory › magnetic random access memory
STT-MRAM |
0.6 | 1 | 2022 | STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Energy-efficient computing › low-power design
power optimization |
0.2 | 1 | 2022 | STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
multicontext-aware CAD flow · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | STT-MRAM-Based Multicontext FPGA for Multithreading Computing EnvironmentabstractThe demand for high-performance computing and rapidly increasing power consumption has increased the necessity for application-specific accelerators. In the datacenter and mobile system, more applications are increasingly relying on accelerators. Field-programmable gate arrays (FPGAs) emerge as a good candidate because they have high programmability and power efficiency. As the number of applications requiring acceleration increases, there is huge demand for FPGAs that support multiple contexts. Previous FPGA designs that support multicontext have various shortcomings such as volatility, poor power efficiency, large performance, area, and reconfiguration overhead. In this article, we propose a spin-transfer torque magnetic RAM (STT-MRAM)-based nonvolatile multicontext FPGA (NVMC-FPGA) that overcomes these shortcomings. We introduce the NVMC-FPGA architecture and operation modes that take advantage of nonvolatility and support multicontext. We also develop the multicontext-aware FPGA computer aided design flow to make the most of the NVMC-FPGA. Compared to the conventional SRAM-based FPGA, when eight identical circuits are mapped, the NVMC-FPGA improves the performance by 15.3% on average and reduces the power consumption by 11.2%–80.7%, depending on the number of simultaneously activated circuits. Moreover, when eight different circuits are mapped, the NVMC-FPGA improves the performance by 58.5% on average and reduces the power consumption by 6.2%–63.3%, depending on the number of simultaneously activated circuits. Jeongbin Kim 0001, Yongwoon Song, Kyungseon Cho, Hyuk-Jun Lee, Hongil Yoon, Eui-Young Chung |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |