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Lingyu Dong

dblp:196/7040 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2023
0000-0003-0919-553XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 61% GPUs and heterogeneous computing · 30% Parallel and multicore computing · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing › GPU computing
GPU algorithms
0.712023
Efficient Algorithm Design of Optimizing SpMV on GPU · HPDC 2023
High-performance computing › sparse linear algebra
sparse matrix computation
0.712023
Efficient Algorithm Design of Optimizing SpMV on GPU · HPDC 2023
High-performance computing › sparse linear algebra › sparse matrix computation
sparse matrix-vector multiplication
0.712023
Efficient Algorithm Design of Optimizing SpMV on GPU · HPDC 2023
Parallel and multicore computing
load balancing
0.212023
Efficient Algorithm Design of Optimizing SpMV on GPU · HPDC 2023

Methods — techniques the papers use, named apart from their topics

adaptive algorithm selection · 0.7
YearPublicationVenuePosition
2023 Efficient Algorithm Design of Optimizing SpMV on GPU
abstract
Sparse matrix-vector multiplication (SpMV) is a fundamental building block for various numerical computing applications. However, most existing GPU-SpMV approaches may suffer from either long preprocessing overhead, load imbalance, format conversion, bad memory access patterns. In this paper, we proposed two new SpMV algorithms:flat andline-enhance, as well as their implementations, for GPU systems to overcome the above shortcomings. Our algorithms work directly on the CSR sparse matrix format. To achieve high performance: 1) for load balance, theflat algorithm uses non-zero splitting andline-enhance uses a mix of row and non-zero splitting; 2) memory access patterns are designed for both algorithms for data loading, storing and reduction steps; and 3) an adaptive approach is proposed to select appropriate algorithm and parameters based on matrix characteristics.
Genshen Chu, Yuanjie He, Lingyu Dong, Zhezhao Ding, He Bai 0005, Changjun Hu
HPDC3
2022 An efficient sparse stiffness matrix vector multiplication using compressed sparse row storage format on AMD GPU
abstract
Summary The performance of sparse stiffness matrix‐vector multiplication is essential for large‐scale structural mechanics numerical simulation. Compressed sparse row (CSR) is the most common format for storing sparse stiffness matrices. However, the high sparsity of the sparse stiffness matrix makes the number of nonzero elements per row very small. Therefore, the CSR‐scalar algorithm, light algorithm, and HOLA algorithm in the calculation will cause some threads in the GPU to be in idle state, which will not only affect the computing performance but also waste computing resources. In this article, a new algorithm, CSR‐vector row, is proposed for fine‐grained computing optimization based on the AMD GPU architecture on heterogeneous supercomputers. This algorithm can set a vector to calculate a row based on the number of nonzero elements of the stiffness matrix. CSR‐vector row has efficient reduce operations, deep memory access optimization, better memory access, and calculation overlapping kernel function configuration scheme. The access bandwidth of the algorithm on AMD GPU is more than 700 GB/s. Compared with CSR‐scalar algorithm, the parallel efficiency of CSR‐vector row is improved by 7.2 times. And floating‐point computing performance is 41%–95% higher than that of light algorithm and HOLA algorithm. In addition, CSR‐vector row is used to calculate the examples from CFD, electromagnetics, quantum chemistry, power network, and semiconductor process, the memory access bandwidth and double floating‐point performance are also improved compared with rocSPARSE‐CSR‐vector.
Longyue Xing, Zhaoshun Wang, Zhezhao Ding, Genshen Chu, Lingyu Dong
Concurr. Comput. Pract. Exp.5