Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-temperature data at 295K to 4K and 40mK data.

Electron-spin qubits in silicon are one of the most promising platforms for implementing large-scale quantum computing. In this platform, a qubit, i.e., the basic unit of quantum information, is associated with the spin of a single electron confined in a region of silicon called a quantum dot. Electron-spin qubit devices must be operated at the cryogenic temperature of 40mK in a 3He/4He dilution refrigerator. This requirement results in long cool-down (“soak”) times and increased costs, which slow down the technology development. Our research aims at developing a high-volume, room-temperature screening technique to assess quantum dots variability and select suitable candidates for mK measurements. In this paper, we present transistor measurement data of quantum dots across a 300mm wafer at temperatures ranging from 300K down to 225K. We analyze the statistical distributions of transistor metrics to detect outliers across temperatures, and hence to prevent wasting measurement time and resources at mK on known bad devices. From the collected data, we conclude that among the metrics analyzed, the threshold voltage appears to be the preferred metric for an effective pre-screening of silicon quantum dots.

Quantum computers based on superconducting qubits have emerged as a leading candidate for a scalable quantum processor architecture. The core of a quantum processor consists of quantum devices that are manipulated using classical electronic circuits, which need to be co-designed for optimal performance and operation. As the principles governing the behavior of the classical circuits and the quantum devices are different, this presents a unique challenge in terms of the simulation, design and optimization of the joint system. A methodology is presented to transform the behavior of small-scale quantum processors to equivalent circuit models that are usable with classical circuits in a generic electrical simulator, enabling the detailed analysis of the impact of many important non-idealities. The methodology has specifically been employed to derive a circuit model of a superconducting qubit interacting with the quantized electromagnetic field of a superconducting resonator. Based on this technique, a comprehensive analysis of the qubit operation is performed, including the coherent control and readout of the qubit using electrical signals. Furthermore, the effect of several non-idealities in the system such as qubit relaxation, decoherence and leakage out of the computational subspace are captured, in contrast to previous works. As the presented method enables the co-simulation of the control electronics with the quantum system, it facilitates the design and optimization of near-term superconducting quantum processors.