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Pascal Pieper
dblp:197/5009
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5ranked-venue papers
4as first author
3since 2021 · last 2022
0000-0002-7155-2537ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 first-author · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Verifying SystemC TLM peripherals using modern C++ symbolic execution toolsabstractIn this paper we propose an effective approach for verification of real-world SystemC TLM peripherals using modern C++ symbolic execution tools. We designed a lightweight SystemC peripheral kernel that enables an efficient integration with the modern symbolic execution engine KLEE and acts as a drop-in replacement for the normal SystemC kernel on pre-processed TLM peripherals. The pre-processing step essentially replaces context switches in SystemC threads with normal function calls which can be handled by KLEE. Our experiments, using a publicly available RISC-V specific interrupt controller, demonstrate the scalability and bug hunting effectiveness of our approach. Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler |
DAC | 1 |
| 2022 | Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual PrototypeabstractRISC-V is a modern Instruction Set Architecture (ISA) that by its open nature in combination with a clean and modular design has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes (VPs) have been introduced into the RISC-V ecosystem to lay the foundation for advanced industry-proven system-level use-cases. However, a VP-driven environment modeling and interaction has been mostly neglected in the RISC-V context. Pascal Pieper, Vladimir Herdt, Rolf Drechsler |
ACM Great Lakes Symposium on VLSI | 1 |
| 2021 | Minimally Invasive HW/SW Co-debug Live Visualization on Architecture LevelabstractWe present a tool that allows developers to debug hard- and software and their interaction in an early design stage. We combine a SystemC virtual prototype (VP) with an easily configurable and interactive graphical user interface and a standard software debugger. The graphical user interface visualizes the internal state of the hardware. At the same time, the software debugger monitors and allows to manipulate the state of the software. This co-visualization supports design understanding and live debugging of the HW/SW interaction. We demonstrate its usefulness with a case-study where we debug an OLED display driver running on a RISC-V VP. Pascal Pieper, Ralf Wimmer 0001, Gerhard Angst, Rolf Drechsler |
ACM Great Lakes Symposium on VLSI | 1 |
| 2020 | Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual PrototypesabstractAvoiding security vulnerabilities is very important for embedded systems. Dynamic Information Flow Tracking (DIFT) is a powerful technique to analyze SW with respect to security policies in order to protect the system against a broad range of security related exploits. However, existing DIFT approaches either do not exist for Virtual Prototypes (VPs) or fail to model complex hardware/software interactions.In this paper, we present a novel approach that enables early and accurate DIFT of binaries targeting embedded systems with custom peripherals. Leveraging the SystemC framework, our DIFT engine tracks accurate data flow information alongside the program execution to detect violations of security policies at run-time. We demonstrate the effectiveness and applicability of our approach by extensive experiments. Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler |
DAC | 1 |
| 2020 | RISC-V based virtual prototype: An extensible and configurable platform for the system-level
Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler |
J. Syst. Archit. | 3 |