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Jaemyung Lim

dblp:197/7372 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
0000-0002-1073-1304ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 81% Memory systems · 19%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › DRAM
DRAM architecture
1.012026
Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation › physical design › power grid analysis
IR drop analysis
1.012026
Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation
physical design
1.012026
Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation › physical design
power delivery network design
1.012026
Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Electronic design automation
power integrity
1.012026
Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

simplified modeling · 1.0iterative analysis · 1.0
YearPublicationVenuePosition
2026 Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN
abstract
In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.
Jinhoon Hyun, In-Chul Jeong, Shinho Chu, Jaemyung Lim
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4