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Marzieh Barkhordar

dblp:198/2203 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 44% High-performance computing · 44% Electronic design automation · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
GPU architecture
0.512021
Efficient Nearest-Neighbor Data Sharing in GPUs · ACM Trans. Archit. Code Optim. 2021
High-performance computing
stencil computation
0.512021
Efficient Nearest-Neighbor Data Sharing in GPUs · ACM Trans. Archit. Code Optim. 2021
Electronic design automation › high-level synthesis › resource binding
register allocation
0.112021
Efficient Nearest-Neighbor Data Sharing in GPUs · ACM Trans. Archit. Code Optim. 2021

Methods — techniques the papers use, named apart from their topics

cycle-accurate simulation · 0.5compiler-allocated registers · 0.5
YearPublicationVenuePosition
2021 Efficient Nearest-Neighbor Data Sharing in GPUs
abstract
Stencil codes (a.k.a. nearest-neighbor computations) are widely used in image processing, machine learning, and scientific applications. Stencil codes incur nearest-neighbor data exchange because the value of each point in the structured grid is calculated as a function of its value and the values of a subset of its nearest-neighbor points. When running on Graphics Processing Unit (GPUs), stencil codes exhibit a high degree of data sharing between nearest-neighbor threads. Sharing is typically implemented through shared memories, shuffle instructions, and on-chip caches and often incurs performance overheads due to the redundancy in memory accesses. In this article, we propose Neighbor Data (NeDa), a direct nearest-neighbor data sharing mechanism that uses two registers embedded in each streaming processor (SP) that can be accessed by nearest-neighbor SP cores. The registers are compiler-allocated and serve as a data exchange mechanism to eliminate nearest-neighbor shared accesses. NeDa is embedded carefully with local wires between SP cores so as to minimize the impact on density. We place and route NeDa in an open-source GPU and show a small area overhead of 1.3%. The cycle-accurate simulation indicates an average performance improvement of 21.8% and power reduction of up to 18.3% for stencil codes in General-Purpose Graphics Processing Unit (GPGPU) standard benchmark suites. We show that NeDa’s performance is within 13.2% of an ideal GPU with no overhead for nearest-neighbor data exchange.
Negin Mahani, Mohammad Sadrosadati, Hajar Falahati, Marzieh Barkhordar, Mario Drumond, Hamid Sarbazi-Azad, Babak Falsafi
ACM Trans. Archit. Code Optim.4