Physical unclonable functions (PUFs) provide a promising solution for enhancing security and device authentication. Strong PUFs can generate quantities of challenge-response pairs(CRPs) but are vulnerable to machine learning (ML) attacks. Weak PUFs must restrict direct access to the original response because they have limited CRPs. In this article, we present a Shuffled Chaotic-dual-PUF structure(SCD-PUF) to defeat against ML attacks. Its working procedure is divided into two main stages: In the first phase, the weak PUF is used to generate secret bits as parameters for the chaotic configuration and along with the secret bits generated by the chaotic process, serve as the obfuscation configuration for the second phase. The second stage involves the Knuth-Durstenfeld shuffle algorithm, concatenation and XOR operations to obfuscate the challenges and responses at the same time. To prove the effectiveness of our proposal, we implement an example of SCD-PUF using Static Random-Access Memory(SRAM) PUF and Arbiter PUF(APUF) on Xilinx ZedBoard FPGAs. Using Logistic Regression (LR), Support Vector Machine (SVM), and Artificial Neural Networks (ANN) as attacking methods, the learning accuracy is maintained at around 51% even when the training data increase to one million, which proves our proposal has enough resistance to ML attacks. Also, the area overhead of our proposal is appropriate and acceptable.

With the separation of design and manufacture in semiconductor industry, self-designed circuits are exposed to hardware Trojan attacks when they are outsourced to an untrustworthy foundry. Trojans activated by digital logic have gained extensive attention. However, those with analog trigger component remain as a serious issue such as the A2 Trojan. Existing defense against A2 Trojans mainly relies on runtime detection mechanism which needs large monitor hardware overhead and complicated identification/handling software. To address these limitations, this article proposes a built-in structure to accelerate the activation of A2 Trojans, which consists of several composite-logic ring oscillators and a multiple-purpose controller. In addition, two post-fabrication detection schemes named time-division mode-switching (TDMS) and scan-based fault test compatible (SFTC) are proposed. TDMS detection scheme can discover A2 Trojans when running functional patterns by inserting oscillating operations every other cycle. SFTC detection scheme can detect A2 Trojans during scan-based fault test by introducing oscillation before each capture operation. Evaluations across a wide range of A2 Trojans and benchmarks show that our proposal is more power-efficient and area-saving compared with existing monitor structure.