Ultra-dense three-dimensional integrated circuits (3D ICs) promise substantial benefits in energy efficiency, throughput, and compute density. However, the number of compute tiers is limited by thermal constraints, which are exacerbated by inter-layer dielectrics (ILD) with low thermal conductivities. We introduce ultra-thin, vertically textured hexagonal boron nitride (h-BN) as a thermal dielectric for 3D IC thermal management. A VLSI-scale RF-sputtering process is used to grow back-end-of-line (BEOL) vertical h-BN on 100 mm wafers at temperatures up to 400°C, yielding a through-plane thermal conductivity of 57 W/m•K. 3D thermal simulations show that this material enables nine high-power 3D-compute tiers (approximately 104 W/cm2per tier) while maintaining peak temperatures below 125°C without increasing footprint. Furthermore, orienting the h-BN vertically (high through-plane thermal conductivity) compared to conformal h-BN (high in-plane thermal conductivity) achieves the same nine-tier stack with only 30% inter-layer dielectric fill, whereas conformal h-BN requires full ILD replacement. These results position vertical h-BN as a BEOL-compatible and VLSI-manufacturable thermal dielectric to enable the next generation of ultra-dense monolithic 3D ICs.

Ultra-dense 3D ICs, with ultra-dense 3D connections (pitch ≤ 100 nm), are projected to achieve large energy and throughput benefits compared to today's ICs. To enable many high-power compute engines on 3D tiers, 3D thermal and power delivery challenges must be overcome. We use a recent idea called 3D thermal scaffolding to overcome both challenges simultaneously. 3D thermal scaffolding cools ultra-dense 3D ICs (e.g., monolithic 3D ICs) using a combination of (1) a new thermally conductive dielectric (the 'thermal dielectric'), (2) scaffolding vias for heat conduction paths to the heat sink, and (3) efficient (and experimentally demonstrated) heatsinks. In this paper, we present new algorithms which place scaffolding vias and the thermal dielectric with minimal footprint impact while satisfying peak temperature and worst-case IR drop constraints. These algorithms are implemented during physical design and demonstrated using a 12-tier open-source 7nm AI accelerator design. Compared to approaches that do not consider power delivery and thermal constraints simultaneously, our approach reduces the footprint penalty due to 3D thermal scaffolding from 10% to 5.5%---an 80% improvement---and simultaneously meets worst-case IR drop constraint of ≤20 mV at 0.7V supply and peak temperature constraint of ≤125°C.

This paper focuses on iso-on-chip-memory-capacity and iso-footprint Energy-Delay-Product (EDP) benefits of ultra-dense 3D, e.g., monolithic 3D (M3D), computing systems vs. corresponding 2D designs. Simply folding existing 2D designs into corresponding M3D physical designs yields limited EDP benefits$(\sim 1.4\times)$. New M3D architectural design points that exploit M3D physical design are crucial for large M3D EDP benefits. We perform comprehensive architectural exploration and detailed M3D physical design using foundry M3D process design kit and standard cell library for front-end-of-line (FEOL) Si CMOS logic, on-chip back-end-of-line (BEOL) memory, and a single layer of on-chip BEOL FETs. We find new M3D AI/ML accelerator architectural design points that have iso-footprint, iso-on-chip-memory-capacity EDP benefits ranging from$5.3\times$to$11.5\times$vs. corresponding 2D designs (containing only FEOL Si CMOS and on-chip BEOL memory). We also present an analytical framework to derive architectural insights into these benefits, showing that our principles extend to many architectural design points across various device technologies.

Carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the energy efficiency of very-large-scale integrated (VLSI) systems. However, multiple challenges have prevented VLSI CNFET circuits from being realized, including inherent nano-scale material defects, robust processing for yielding complementary CNFETs (i.e., CNT CMOS: including both PMOS and NMOS CNFETs), and major CNT variations. Here, we summarize techniques that we have recently developed to overcome these outstanding challenges, enabling VLSI CNFET circuits to be experimentally realized today using standard VLSI processing and design flows. Leveraging these techniques, we demonstrate the most complex CNFET circuits and systems to-date, including a three-dimensional (3D) imaging system comprising CNFETs fabricated directly on top of a silicon imager, CNT CMOS analog and mixed-signal circuits, 1 kilobit CNFET static random-access memory (SRAM) memory arrays, and a 16-bit RISC-V microprocessor built entirely out of CNFETs.