Yangtao Dong

dblp:198/5627 · DBLP profile ↗
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6ranked-venue papers
3as first author
4since 2021 · last 2024
0000-0001-9565-4688ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 3 first-author · 4 since 2021
YearPublicationVenuePosition
2024 A 0.6 V, 1.74 mW, 2.9 dB NF Inductorless Wideband LNA in 28-nm CMOS Exploiting Noise Cancellation and Current Reuse
abstract
This paper proposes an inductorless wideband common-gate (CG)-common-source (CS) noise-cancelling (NC) low-noise amplifier (LNA) with current reuse (CR) for ultra-low voltage (ULV) application. In the conventional NC LNA with CR, to reuse the DC current of the auxiliary amplifier, three transistors are stacked in a single branch, leading to a reduced voltage headroom. Moreover, additional inductor and capacitors are required, resulting in a large silicon area. In the proposed work, the DC current of the auxiliary amplifier can be reused without using any inductor. Meanwhile, only two transistors are stacked in a single branch, making it suitable for ULV application. Fabricated in 28 nm CMOS, this work exhibits a voltage gain of 20 dB with a 3-dB bandwidth of 0.2 to 2.85 GHz, a minimum NF of 2.9 dB at 1.7 GHz and an IIP3 of -12.3 dBm at 1 GHz. It consumes 1.74 mW from a 0.6 V supply and occupies a very compact die area of 0.0048 mm2.
Zhe Liu 0038, Chirn Chye Boon, Yangtao Dong
IEEE Trans. Circuits Syst. I Regul. Pap.3
2021 A Cross-Coupled Pair Regeneration Based dB-Linear Programable Gain Amplifier with THD Enhancement
abstract
This paper reports a cross-coupled pair regeneration based programmable gain amplifier (CCPR- PGA) with an improved total harmonic distortion (THD) performance. By utilizing the ping-pong technique, two identical conventional CCPR-PGAs are operating alternatively. These two CCPR-PGAs connect to the output of the overall PGA only at their hold state, as a result, the ripples generated during the processes of reset, sample and regeneration are effectively suppressed. Simulated in 28-nm CMOS technology, the proposed PGA achieves a gain range of 45.4 dB with a gain error of ± 0.3 dB. The bandwidth of the proposed PGA reaches 40 MHz with a clock frequency of 100 MHz. Moreover, the THD performance is improved by 25.8 dB at 1 MHz and 17.6 dB at 10 MHz when compared to the conventional structure. The overall PGA consumes 460 μA current from a supply voltage of 0.9 V.
Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Ao Zhou 0003, Xin Ding 0003
ISCAS1
2021 Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer
abstract
The recent development of wafer-level, low-cost packaging platforms based on the silicon interposer and direct wafer bonding has paved a new way toward high-performance millimeter-wave to terahertz 2.5/3D heterogeneous integration, enabling high-speed wireless communication and chip-to-chip interconnects. Using this emerging technology, several passive components are studied in this paper toward the terahertz applications. One 240 GHz distributed mushroom antenna is designed using interposers to form multiple resonances unit- cell, achieving 7.16 dBi gain with 76% radiation efficiency. A 300 GHz differential patch antenna is designed, delivering 5.6 dBi gain with 88% radiation efficiency. A 60 GHz directional coupler based on interleaving topology is proposed and simulated, showing a 3.3 dB coupling factor with more than 30 GHz bandwidth. These preliminary results reveal a promising solution by using the wafer-to-wafer packaging platform to build high-performance passive building blocks.
Yuan Liang 0004, Chirn Chye Boon, Qian Chen 0027, Yangtao Dong
ISCAS4
2021 A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation
abstract
This brief presents a bidirectional nonlinearly coupled quadrature voltage-controlled oscillator (BNC-QVCO) incorporating passive phase interpolation for the generation of multiphase signals. In addition, to generate multiphase signals, the proposed bidirectional nonlinearly coupling network improves the phase noise performance of the QVCO by producing approximate-in-phase injection-coupling currents into the LC tank. Moreover, to balance the amplitude of eight-phase signals, an additional passive amplitude division circuit is implemented with capacitor banks for calibration. For verification, a BNC-QVCO incorporating passive phase interpolation is implemented in a 40-nm CMOS technology with a core area of 0.13 mm2. The measured multiphase signals achieve a phase noise of -116.57 dBc/Hz at 1-MHz offset from 4.32 GHz. The power consumption without buffers is 10.2 mW under 1-V supply voltage and a 20% frequency tuning range from 4 to 4.8 GHz is achieved with the implemented digitally controlled capacitor banks.
Yangtao Dong, Chirn Chye Boon, Xin Ding 0003, Chenyang Li 0008, Zhe Liu 0038
IEEE Trans. Very Large Scale Integr. Syst.1
2020 Robust Seizure Prediction Based on Multivariate Empirical Mode Decomposition and Maximum Synchronization Modularity
abstract
Reliable and timely seizure prediction has been increasingly helpful and indispensable for epileptic patients, ensuring safety and improving life quality. Based on electroencephalogram (EEG), a new patient-specific seizure prediction method is proposed in this paper to detect impending seizures automatically and accurately, using a novel indicator called maximum synchronization modularity. As the first step towards this goal, raw EEG signals are decomposed by multivariate empirical mode decomposition (MEMD). Then graph community detection algorithm is applied to characterize the phase synchronization modularity of sub-band EEG signals. Thus, the deep interaction of scalp electrical activity can be effectively revealed. Finally, radial basis function neural network (RBFNN) is used for the classification. The proposed method achieves an average prediction accuracy of 99.06% and an average sensitivity of 100% on CHB-MIT scalp EEG database, outperforming related works based on the same database.
Lihan Tang, Menglian Zhao, Yangtao Dong
IECON4
2017 A 1.8 μW 32 nV/√Hz current-reuse capacitively-coupled instrumentation amplifier for EEG detection
abstract
This paper presents a capacitively-coupled chopper instrumentation amplifier (CCIA) for portable EEG detection devices. In this design, the current-reuse technology is adopted in the core amplifier and the ripple reduction loop (RRL) to cut down the power consumption of the whole system. A novel ripple reduction loop based on ping-pong auto-zeroing topology is proposed to reduce the ripple at the output of the CCIA. It makes the chopping ripple be attenuated about 46 dB. This system is simulated in a 0.18 μm CMOS process. Simulation results show that the proposed CCIA achieves an equivalent input noise power spectrum density (PSD) of 32 nV/VHz, a noise efficiency factor (NEF) of 1.7, CMRR of 90 dB. The overall current consumption is 1.8 μΑ at a 1V supply.
Yangtao Dong, Lihan Tang, Menglian Zhao
ISCAS1