This paper proposes a high in-band (IB) linearity gain-boosted N-path filter with bandwidth (BW)-extended. The proposed filter uses a gain-boosted design, where a switched postposition gm-C network achieves the bandpass-bandreject (BPF-BRF) cascade response. This setup selectively enhances the gain-boosted filter's transition band and extends the filter's bandwidth. Fabricated in 130nm SOI CMOS, our proposed filter realizes a 4.0-5.5 dB gain and a 6.89-8.01 dB noise figure (NF) over a 0.1-1.1 GHz tuning range. With postposition gmlinearity and clock boost circuit optimization, our filter at 0.5 GHz exhibits an in-band input-referred −1dB compression point (IB-ICP-1dB) of 0.21 dBm and an in-band input-referred 3rd-order intercept point (IB-IIP3) of 12.59 dBm and an out-of-band (OOB)-IIP3 of 17.28 dBm. The power consumption is 36-74 mW. The chip active area is 0.9 mm2.

This paper presents a dual-mode offset calibration for high-speed dynamic comparators, offering a wide calibration range, low offset, low input-referred noise, and reduced comparison delay. A wide calibration range is achieved in Mode 1 by using a switched-capacitor-biased auxiliary differential current path, while a low-noise, high-precision calibration with reduced comparison delay is provided by Mode 2 using digitally adjustable cross-coupled capacitors which enhance the transconductance of the differential pairs in the pre-amplifier. Designed in a 28-nm CMOS process, simulation results show that at an operating frequency of 4 GHz, the tuning range is from -31.5 to 35.4 mV, with the standard deviation of comparator offset reduced from 8.06 mV to 136 μV. When the two modes are configured to operate synergistically, the input-referred noise is 269 μV with a comparison delay of less than 19.3 ps. Furthermore, the additional power consumption due to the calibration circuits is less than 12%.

Non-Volatile Memory (NVM) has emerged as an alternative to next-generation main memories. Although many tree indices have been proposed for NVM, they generally use B+-tree-like structures. To further improve the performance of NVM-aware indices, we consider integrating learned indexes into NVM. The challenges of such an integration are two fold: (1) existing NVM indices rely on small nodes to accelerate insertions with crash consistency, but learned indices use huge nodes to obtain a flat structure. (2) the node structure of learned indices is not NVM friendly, meaning that accessing a learned node will cause multiple NVM block misses. Thus, in this paper, we propose a new persistent learned index called PLIN. The novelty of PLIN lies in four aspects: an NVM-aware data placement strategy, locally unordered and globally ordered leaf nodes, a model copy mechanism, and a hierarchical insertion strategy. In addition, PLIN is proposed for the NVM-only architecture, which can support instant recovery. We also present optimistic concurrency control and fine-grained locking mechanisms to make PLIN scalable to concurrent requests. We conduct experiments on real persistent memory with various workloads and compare PLIN with APEX, PACtree, ROART, TLBtree, and Fast&Fair. The results show that PLIN achieves 2.08x higher insertion performance and 4.42x higher query performance than its competitors on average. Meanwhile, PLIN only needs ~30 μs to recover from a system crash.

On-line decision augmentation (OLDA) has been considered as a promising paradigm for real-time decision making powered by Artificial Intelligence (AI). OLDA has been widely used in many applications such as real-time fraud detection, personalized recommendation, etc. On-line inference puts real-time features extracted from multiple time windows through a pre-trained model to evaluate new data to support decision making. Feature extraction is usually the most time-consuming operation in many OLDA data pipelines. In this work, we started by studying how existing in-memory databases can be leveraged to efficiently support such real-time feature extractions. However, we found that existing in-memory databases cost hundreds or even thousands of milliseconds. This is unacceptable for OLDA applications with strict real-time constraints. We therefore propose FEDB ( F eature E ngineering D ata b ase), a distributed in-memory database system designed to efficiently support on-line feature extraction. Our experimental results show that FEDB can be one to two orders of magnitude faster than the state-of-the-art in-memory databases on real-time feature extraction. Furthermore, we explore the use of the Intel Optane DC Persistent Memory Module (PMEM) to make FEDB more cost-effective. When comparing the proposed PMEM-optimized persistent skiplist to the FEDB using DRAM+SSD, PMEM-based FEDB can shorten the tail latency up to 19.7%, reduce the recovery time up to 99.7%, and save up to 58.4% total cost of a real OLDA pipeline.