Dynamic Voltage and Frequency Scaling (DVFS) is an effective means to reduce the energy dissipation of digital designs. While on most commodity FPGAs, memory and processor have separately controlled voltages, the programmable logic section relies on a single voltage rail and thus imposes the same voltage for all hardware accelerators that operate concurrently. Finding time slots eligible for voltage scaling gets difficult in virtualized systems, where the FPGA is shared by tasks executed in multiple guest operating systems. The situation gets even more complicated, when error-tolerant tasks are considered that allow the voltage to be reduced below its nominal value, which could provoke a certain rate of faulty hardware accelerator runs. As a solution, we propose a strategy that synchronizes concurrently executed periodic hardware tasks under consideration of their reliability as well as their real-time requirements so that the supply voltage is controlled accordingly. The proposed strategy can be combined with further mechanisms for saving energy. Our run-time module performs clock gating and adjusts the voltage to the requirements of aperiodic tasks. For fault-tolerant tasks, we monitor the error rate using Algorithm Based Fault Tolerance (ABFT) that can detect and characterize errors with an accuracy close to $100 \%$. Compared to a strategy that scales voltage without synchronizing hardware tasks, we achieve in the best case a power saving by $29.4 \%$ and an average saving by $7 \%$.

A major concern with battery-operated devices is power-awareness and its appropriate computing. The power dissipation of such systems is usually considered a hardware problem. However, it can be solved by implementing power-aware techniques. Such algorithms have shown promise as an approach to dynamically adjust the power consumption of embedded systems within feasible ranges. One of the most popular power-saving techniques is Dynamic Voltage and Frequency Scaling (DVFS). Besides the power management, an accurate and fast power monitoring service is necessary on embedded platforms to reduce power consumption. In this paper, we provide an overview of power-aware computing platforms based on different application domains. It intends to summarize recently published research results related to power-aware computing architectures using Field Programmable Gate Arrays (FPGAs). We identify trends and highlight key future directions for power management techniques and power monitoring services.

Real-time Operating Systems (RTOSs) are mainly implemented in software and sequentially executed on processors. The periodic call of the task scheduling service introduces additional overhead in software and eventually leads to jitter. However, the occurring overhead can be shortened or eliminated by using reconfigurable systems. Besides, dynamically adjusting power dissipation of reconfigurable systems leads to a change in the execution time of applications, so deadlines may not be met. Therefore, careful study of the impact of such optimizations on real-time capabilities is needed. The presented PhD project deals with offloading of RTOS components considering power dissipation on reconfigurable platforms. For this purpose, the task scheduling of FreeRTOS has already been offloaded to a co-processor while scaling voltage and frequency on XC7Z020. This reduced the execution time of the task scheduling by 38.9%.