Radio remains a pervasive medium for mass information dissemination, with AM/FM stations reaching more Americans than either smartphone-based social networking or live television.Increasingly, radio broadcasts are also streamed online and accessed over the Internet.We present WavePulse, a framework that records, documents, and analyzes radio content in real-time.While our framework is generally applicable, we showcase the efficacy of WavePulse in a collaborative project with a team of political scientists focusing on the 2024 Presidential Election.We use WavePulse to monitor livestreams of 396 news radio stations over a period of three months, processing close to 500,000 hours of audio streams.These streams were converted into time-stamped, diarized transcripts and analyzed to answer key political science questions at both the national and state levels.Our analysis revealed how local issues interacted with national trends, providing insights into information flow.Our results demonstrate WavePulse's efficacy in capturing and analyzing content from radio livestreams sourced from the Web.Code and dataset can be accessed at https://wave-pulse.io

Representing 3D objects and scenes with neural radiance fields has become very popular over the last years. Recently, surface-based representations have been proposed, that allow to reconstruct 3D objects from simple photographs. However, most current techniques require an accurate camera calibration, i.e. camera parameters corresponding to each image, which is often a difficult task to do in real-life situations. To this end, we propose a method for learning 3D surfaces from noisy camera parameters. We show that we can learn camera parameters together with learning the surface representation, and demonstrate good quality 3D surface reconstruction even with noisy camera observations.

Analytical and practical evidence indicates the advantage of quantum computing solutions over classical alternatives. Quantum-based heuristics relying on the variational quantum eigensolver (VQE) and the quantum approximate optimization algorithm (QAOA) have been shown numerically to generate high-quality solutions to hard combinatorial problems, yet incorporating constraints to such problems has been elusive. To this end, this work puts forth a quantum heuristic to cope with stochastic binary quadratically constrained quadratic programs (QCQP). Identifying the strength of quantum circuits to efficiently generate samples from probability distributions that are otherwise hard to sample from, the variational quantum circuit is trained to generate binaryvalued vectors to approximately solve the aforesaid stochastic program. The method builds upon dual decomposition and entails solving a sequence of judiciously modified standard VQE tasks. Tests on several synthetic problem instances using a quantum simulator corroborate the near-optimality and feasibility of the method, and its potential to generate feasible solutions for the deterministic QCQP too.

The human brain has evolved to perform complex and computationally expensive cognitive tasks, such as audio-visual perception and object detection, with ease. For instance, the brain can recognize speech in different dialects and perform other cognitive tasks, such as attention, memory, and motor control, with just 20 W of power consumption. Taking inspiration from neural systems, we propose a low-power neuromorphic hardware architecture to perform classification on temporal data at the edge. The proposed architecture uses a neuromorphic cochlea model for feature extraction and reservoir computing (RC) framework as a classifier. In the proposed hardware architecture, the RC framework is modified for on-the-fly generation of reservoir connectivity, along with binary feedforward and reservoir weights. Also, a large reservoir is split into multiple small reservoirs for efficient use of hardware resources. These modifications reduce the computational and memory resources required, thereby resulting in a lower power budget. The proposed classifier is validated for speech and human activity recognition (HAR) tasks. We have prototyped our hardware architecture using Intel's cyclone-10 low-power series field-programmable gate array (FPGA), consuming only 4790 logic elements (LEs) and 34.9-kB memory, making it a perfect candidate for edge computing applications. Moreover, we have implemented a complete system for speech recognition with the feature extraction block (cochlea model) and the proposed classifier, utilizing 15 532 LEs and 38.4-kB memory. By using the proposed idea of multiple small reservoirs along with on-the-fly generation of reservoir binary weights, our architecture can reduce the power consumption and memory requirement by order of magnitude compared to existing FPGA models for speech recognition tasks with similar complexity.

A major challenge in modern neural networks is the utilization of previous knowledge for new tasks in an effective manner, otherwise known as transfer learning. Fine-tuning, the most widely used method for achieving this, suffers from catastrophic forgetting. The problem is often exacerbated in natural language processing (NLP). In this work, we assess progressive neural networks (PNNs) as an alternative to fine-tuning. The evaluation is based on common NLP tasks such as sequence labeling and text classification. By gauging PNNs across a range of architectures, datasets, and tasks, we observe improvements over the baselines throughout all experiments.

In opportunistic networks, the path connecting two nodes is not continuous at any time instant. In such an environment, routing is an extremely taxing word owing to the ever‐changing nature of the network and random connections between nodes. Routing in such networks is done by a store carry forward mechanism, in which local information is used to make opportunistic routing decisions. In this study, the authors present a novel dynamic and intelligent self‐learning routing protocol that is an improvement of the history‐based routing protocol for opportunistic (HiBOp) networks. The proposed method presents a novel solution for the estimation of average latency between any two nodes, which is used along with reinforcement learning to dynamically learn the nodes' interactions. Simulation results on a real mobility trace (INFOCOM 2006) show that latency‐aware reinforced routing for opportunistic network applied to HiBOp outperforms the original HiBOp protocol by 14.4% in terms of delivery probability, 15% in terms of average latency and 34.7% in terms of overhead ratio.

Hardware implementation of brain-inspired algorithms such as reservoir computing, neural population coding and deep learning (DL) networks is useful for edge computing devices. The need for hardware implementation of neural network algorithms arises from the high resource utilization in form of processing and power requirements, making them difficult to integrate with edge devices. In this paper, we propose a non-spiking four quadrant current mode neuron model that has a generalized design to be used for population coding, echo-state networks (uses reservoir network), and DL networks. The model is implemented in analog domain with transistors in sub-threshold region for low power consumption and simulated using 180nm technology. The proposed neuron model is configurable and versatile in terms of non-linearity, which empowers the design of a system with different neurons having different activation functions. The neuron model is more robust in case of population coding and echo-state networks (ESNs) as we use random device mismatches to our advantage. The proposed model is current input and current output, hence, easily cascaded together to implement deep layers. The system was tested using the classic XOR gate classification problem, exercising 10 hidden neurons with population coding architecture. Further, derived activation functions of the proposed neuron model have been used to build a dynamical system, input controlled oscillator, using ESNs.

Image segmentation is a critical step in achieving computer vision. For fast and near real time image segmentation it is important to use dedicated hardware as it works much faster as compared to software based solutions. This paper presents a CMOS based real time image segmentation analog circuit using semi-supervised learning scheme. The proposed circuit ensures minimal operating power required when compared to its digital hardware implementation due to sub-threshold region operation of MOSFET and much lesser number of transistors being used. The circuit operation is based upon an anisotropic current spreading in non linear circuits. An analog pixel array is created which takes in weights and initial seed as input and segments the image based on them. Weights are generated from an image based on the feature similarity and are then fed to the pixel array. These weights dictate the anisotropic diffusion of current in the analog array and thus required segmentation is achieved. The proposed analog circuit based segmentation scheme is highly power efficient as compared to digital hardware implementation. Thus this scheme can be used in a power constrained environment as in case of Internet of Things (IoTs) network with independent battery-less nodes. Our approach will also be suitable for applications that require highperformance computing to run in real time, such as biomedical image segmentation for image-guided surgery.