Recently, several parallel frameworks have emerged to utilize the increasing computational capacity of multiprocessors. Parallel tasks are distinguished from traditional sequential tasks in that the subtasks contained in a single parallel task can simultaneously execute on multiple processors. In this study, we consider the scheduling problem of minimizing the number of processors on which the parallel real-time tasks feasibly run. In particular, we focus on scheduling sporadic parallel real-time tasks, in which precedence constraints between subtasks of each parallel task are expressed using a directed acyclic graph (DAG). To address the problem, we formulate an optimization problem that aims to minimize the maximum processing capacity for executing the given tasks. We then suggest a polynomial solution consisting of three steps: (1) transform each parallel real-time task into a series of multithreaded segments, while respecting the precedence constraints of the DAG; (2) selectively extend the segment lengths; and (3) interpret the problem as a flow network to balance the flows on the terminal edges. We also provide the schedulability bound of the proposed solution: it has acapacity augmentation boundof 2. Our experimental results show that the proposed approach yields higher performance than one developed in a recent study.

In this paper, we describe the necessity of VC merging in an edge label switched router (LSR) for scalability, one of the important merits in multi-protocol label switching (MPLS). We introduce the design of a high-speed IP forwarding engine with virtual connection (VC) merging. This forwarding engine largely consists of a segmentation and reassembly (SAR) processing part, a CAM-based IP look-up processing part, a VC-merging part, and a physical line interface part. It provides some desirable characteristics that are described in this paper. We also compare the edge MPLS systems with centralized and distributed forwarding engine architectures, and the good points of the MPLS system with the latter architectures when supporting VC merging.