Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Vahdaneh Kiani

dblp:199/5280 · DBLP profile ↗
← Back
2ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0002-5440-1868ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 56% Memory systems · 44%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
soft errors
0.412019
Enhancing Instruction TLB Resilience to Soft Errors · IEEE Trans. Computers 2019
Hardware reliability and fault tolerance › soft errors
soft error resilience
0.412019
Enhancing Instruction TLB Resilience to Soft Errors · IEEE Trans. Computers 2019
Memory systems › memory management › virtual memory › address translation
TLB
0.412019
Enhancing Instruction TLB Resilience to Soft Errors · IEEE Trans. Computers 2019
Memory systems
cache
0.112019
Enhancing Instruction TLB Resilience to Soft Errors · IEEE Trans. Computers 2019
Memory systems › data locality
spatial locality
0.112019
Enhancing Instruction TLB Resilience to Soft Errors · IEEE Trans. Computers 2019
YearPublicationVenuePosition
2019 Enhancing Instruction TLB Resilience to Soft Errors
abstract
A translation lookaside buffer (TLB) is a type of cache used to speed up the virtual to physical memory translation process. Instruction TLBs store virtual page numbers and their related physical page numbers for the last accessed pages of instruction memory. TLBs like other memories suffer soft errors that can corrupt their contents. A false positive due to an error produced in the virtual page number stored in the TLB may lead to a wrong translation and, consequently, the execution of a wrong instruction that can lead to a program hard fault or to data corruption. Parity or error correction codes have been proposed to provide protection for the TLB, but they require additional storage space. This paper presents some schemes to increase the instruction TLB resilience to this type of errors without requiring any extra storage space, by taking advantage of the spatial locality principle that takes place when executing a program.
Alfonso Sánchez-Macián, Luis Alberto Aranda, Pedro Reviriego, Vahdaneh Kiani, Juan Antonio Maestro
IEEE Trans. Computers4
2017 Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links
Vahdaneh Kiani, Midia Reshadi
J. Supercomput.1