Non-volatile memory (NVM) technologies such as spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM) have significant advantages compared to conventional SRAM due to their non-volatility, higher cell density, and scalability features. While previous work has investigated several architectural implications of NVM for generic applications, in this work we present DeepNVM++, a framework to characterize, model, and analyze NVM-based caches in GPU architectures for deep learning (DL) applications by combining technology-specific circuit-level models and the actual memory behavior of various DL workloads. We present both iso-capacity and iso-area performance and energy analysis for systems whose last-level caches rely on conventional SRAM and emerging STT-MRAM and SOT-MRAM technologies. In the iso-capacity case, STT-MRAM and SOT-MRAM provide up to 3.8x and 4.7x energy-delay product (EDP) reduction and 2.4x and 2.8x area reduction compared to conventional SRAM, respectively. Under iso-area assumptions, STT-MRAM and SOT-MRAM provide up to 2x and 2.3x EDP reduction and accommodate 2.3x and 3.3x cache capacity when compared to SRAM, respectively. We also perform a scalability analysis and show that STT-MRAM and SOT-MRAM achieve orders of magnitude EDP reduction when compared to SRAM for large cache capacities. Our comprehensive cross-layer framework is demonstrated on STT-/SOT-MRAM technologies and can be used for the characterization, modeling, and analysis of any NVM technology for last-level caches in GPUs for DL applications.

Non-volatile memory (NVM) technologies such as spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM) have significant advantages compared to conventional SRAM due to their non-volatility, higher cell density, and scalability features. While previous work has investigated several architectural implications of NVM for generic applications, in this work we present DeepNVM, a framework to characterize, model, and analyze NVM-based caches in GPU architectures for deep learning (DL) applications by combining technologyspecific circuit-level models and the actual memory behavior of various DL workloads. We present both iso-capacity and isoarea performance and energy analysis for systems whose lastlevel caches rely on conventional SRAM and emerging STT-MRAM and SOT-MRAM technologies. In the iso-capacity case, STT-MRAM and SOT-MRAM provide up to 4.2× and 5× energy-delay product (EDP) reduction and 2.4× and 3× area reduction compared to conventional SRAM, respectively. Under iso-area assumptions, STT-MRAM and SOT-MRAM provide 2.3× EDP reduction on average across all workloads when compared to SRAM. Our comprehensive cross-layer framework is demonstrated on STT-/SOT-MRAM technologies and can be used for the characterization, modeling, and analysis of any NVM technology for last-level caches in GPU platforms for deep learning applications.

As CMOS technology continues to scale down due to advances in lithography, the interaction of neighboring patterns is exacerbated. Every pattern printed on silicon is influenced by its neighbors given a technology-specific interaction range. As transistors and cells shrink to sizes of the same order of the interaction range, pattern dependencies at the 16-nm node (and below) make the prediction of functional and parametric yield challenging. Precharacterizing all combinations of layouts as a function of all possible neighboring patterns is impractical due to exponential complexity, whereas silicon characterization of all patterns is practically impossible. In this paper, we propose a virtual characterization vehicle (VCV) methodology that can exhaustively identify all uniquely occurring layout patterns in a standard cell library. VCVs can expose all cell neighboring arrangements as a function of a radius of influence while compiling the pattern frequency and also uncovering the arrangement of cells that create unique patterns. Effects that span multiple layers are also captured in our analysis. VCV results can be used to co-design libraries by suggesting favorable compositions as well as favorable layout styles. Finally, VCVs can be turned into test-chips that are guaranteed to cover all identified patterns with the aid of self-testing features. An extremely regular library was developed in 16-nm FinFET technology and is used to showcase our pattern analysis in which DFM quality is shown to be improved with respect to commercial libraries. Our silicon results demonstrate the feasibility of turning the VCV approach into real silicon test chips.

Spiking neural networks (SNNs) are of interest for applications for which conventional computing suffers from the nearly insurmountable memory-processor bottleneck. This paper presents a stochastic SNN architecture that is based on specialized logic-in-memory synaptic units to create a unique processing system that offers massively parallel processing power. Our proposed synaptic unit consists of strained magnetic tunnel junction (MTJ) devices and transistors. MTJs in our synapse are dual purpose, used as both random bit generators and as general-purpose memory. Our neurons are modeled as integrate-and-fire components with thresholding and refraction. Our circuit is implemented using CMOS 28-nm technology that is compatible with the MTJ technology. Our design shows that the required area for the proposed synapse is only [Formula: see text]. When idle, the synapse consumes 675 pW. When firing, the energy required to propagate a spike is 8.87 fJ. We then demonstrate an SNN that learns (without supervision) and classifies handwritten digits of the MNIST database. Simulation results show that our network presents high classification efficiency even in the presence of fabrication variability.

Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced sub-20-nm CMOS nodes, making low-volume fabrication of integrated circuits (ICs) almost intangible. For ICs in which the cost of design dominates the fabrication, we seek to trade some amount of chip area to lower NRE costs. To this end, we consider designing logic cell layouts for easier routing and DFM closure. We accustom a layout simplification and reuse approach to build standard cell libraries such that good pin access and layout regularity are ensured for all cells. Using a commercial 14-/16-nm technology, we developed two 100-cell logic cell libraries that are, respectively, 9 and 10.5 metal tracks tall. Our routing experiments on multiple designs show that taller cells can endure 20% higher placement density while reducing the number of design rule check (DRC) violations by four orders of magnitude compared with a commercial 7.5 track library. Silicon measurements show that taller cells can enable faster design closure in ICs with stringent performance requirements at the cost of a marginal power overhead. Finally, our logic cell design approach can make advanced CMOS nodes more affordable for low-volume design.

Ultra-low-power sensor nodes enable many new applications and are becoming increasingly pervasive and important. Energy efficiency is the key determinant of the value of these devices: battery-powered nodes want their battery to last, and nodes that harvest energy should minimize their time spent recharging. Unfortunately, current devices are energy-inefficient.