Demo Data from EDBT 2026 / reviewers in the wild / expert
Daniel Peroni
dblp:199/8649 · also Daniel Nikolai Peroni
· DBLP profile ↗
7ranked-venue papers
4as first author
0since 2021 · last 2020
0000-0002-1580-9473ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 4 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Emerging computing paradigms · 43% Integrated circuit design · 25% GPUs and heterogeneous computing · 21% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms
approximate computing |
1.2 | 3 | 2020 | Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 Data Reuse for Accelerated Approximate Warps · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 ARGA: Approximate Reuse for GPGPU Acceleration · DAC 2019 |
Emerging computing paradigms › approximate computing › approximate circuit design
approximate arithmetic circuits |
0.7 | 2 | 2020 | Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing · DAC 2017 |
Integrated circuit design › digital arithmetic circuits
approximate floating-point multiplier |
0.7 | 2 | 2020 | Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing · DAC 2017 |
GPUs and heterogeneous computing
GPU computing |
0.5 | 2 | 2020 | Data Reuse for Accelerated Approximate Warps · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing · DAC 2017 |
Integrated circuit design › digital circuit design › arithmetic circuit design
floating-point unit |
0.4 | 1 | 2020 | Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Hardware accelerators and domain-specific architectures
approximate computing accelerator |
0.4 | 1 | 2019 | ARGA: Approximate Reuse for GPGPU Acceleration · DAC 2019 |
GPUs and heterogeneous computing › GPU computing
GPGPU acceleration |
0.4 | 1 | 2019 | ARGA: Approximate Reuse for GPGPU Acceleration · DAC 2019 |
Energy-efficient computing › power-performance tradeoff
energy-delay product optimization |
0.1 | 1 | 2019 | ARGA: Approximate Reuse for GPGPU Acceleration · DAC 2019 |
GPUs and heterogeneous computing › GPU computing
approximate GPU arithmetic |
0.1 | 1 | 2017 | CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing · DAC 2017 |
Methods — techniques the papers use, named apart from their topics
approximate lookup table · 0.8tiered approximation · 0.4neuron-aware approximation · 0.4multi-table parallel lookup · 0.4dynamic error control · 0.3approximate computing · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Data Reuse for Accelerated Approximate WarpsabstractMany data-driven applications, including computer vision, machine learning, speech recognition, and medical diagnostics show tolerance to computation error. These applications are often accelerated on GPUs, but the performance improvements require high energy usage. In this article, we present DRAAW, an approximate computing technique capable of accelerating GPGPU applications at a warp level. In GPUs, warps are groups of threads which issued together across multiple cores. The slowest thread dictates the pace of the warp, so DRAAW identifies these bottlenecks and avoids them during approximation. We alleviate computation costs by using an approximate lookup table which tracks recent operations and reuses them to exploit temporal locality within applications. To improve neural network performance, we propose neuron aware approximation, a technique which profiles operations within network layers and automatically configures DRAAW to ensure computations with more impact on the output accuracy are subject to less approximation. We evaluate our design by placing DRAAW within each core of an Nvidia Kepler Architecture Titan. DRAAW improves throughput by up to 2.8× and improves energy-delay product (EDP) by 5.6× for six GPGPU applications while maintaining less than 5% output error. We show neuron aware approximation accelerates the inference of six neutral networks by 2.9× and improves EDP by 6.2× with less than 1% impact on prediction accuracy. Daniel Peroni, Mohsen Imani, Hamid Nejatollahi, Nikil Dutt, Tajana Rosing |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2020 | Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point MultiplierabstractMany applications, such as machine learning and sensor data analysis, are statistical in nature and can tolerate some level of inaccuracy in their computation. Approximate computing is a viable method to save energy and increase performance by controllably trading off energy for accuracy. In this paper, we propose a tiered approximate floating point multiplier, called CFPU, which significantly reduces energy consumption and improves the performance of multiplication at a slight cost in accuracy. The floating point multiplication is approximated by replacing the costly mantissa multiplication step of the operation with lower energy alternatives. We process the data by using one of the three modes: a basic approximate mode, an intermediate approximate mode, or on the exact hardware, depending on the accuracy requirements. We evaluate the efficiency of the proposed CFPU on a wide range of applications including twelve general OpenCL ones and three machine learning applications. Our results show that using the first CFPU approximation mode results in 3.5× energy-delay product (EDP) improvement, compared to a GPU using traditional floating point units (FPUs), while ensuring less than 10% average relative error. Adding the second mode further increases the EDP improvement to 4.1×, compared to an unmodified FPU, for less than 10% error. In addition, our results show that the proposed CFPU can achieve 2.8× EDP improvement for multiply operations as compared to state-of-the-art approximate multipliers. Daniel Peroni, Mohsen Imani, Tajana Rosing |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2019 | ALook: adaptive lookup for GPGPU accelerationabstractAssociative memory in form of look-up table can decrease the energy consumption of GPGPU applications by exploiting data locality and reducing the number redundant computations. State of the art architectures utilize associative memory as static look-up tables. Static designs lack the ability to adapt to applications at runtime, limiting them to small segments of code with high redundancy. In this paper, we propose an adaptive look-up based approach, called ALook, which uses a dynamic update policy to maintain a set of recently used operations in associative memory. ALook updates with values computed by floating point units at runtime to adapt to the workload and matches the stored results to avoid recomputing similar operations. ALook utilizes a novel FPU architecture which accelerates GPU computation by parallelizing the operation lookup process. We test the efficiency of ALook on image processing, general purpose, and machine learning applications by integrating it beside FPUs in an AMD Southern Island GPU. Our evaluation shows that ALook provides 3.6X EDP (Energy Delay Product) and 32.8% performance speedup, compared to an unmodified GPU, for applications accepting less than 5% output error. The proposed ALook architecture improves the GPU performance by 2.0X as compared to state-of-the-art computational reuse methods for the same level of output error. Daniel Peroni, Mohsen Imani, Tajana Rosing |
ASP-DAC | 1 |
| 2019 | ARGA: Approximate Reuse for GPGPU AccelerationabstractMany data-driven applications including computer vision, speech recognition, and medical diagnostics show tolerance to error during computation. These applications are often accelerated on GPUs, but high computational costs limit performance and increase energy usage. In this paper, we present ARGA, an approximate computing technique capable of accelerating GPGPU applications. ARGA provides an approximate lookup table to GPGPU cores to avoid recomputing instructions with identical or similar values. We propose multi-table parallel lookup which enables computational reuse to significantly speed-up GPGPU computation by checking incoming instructions in parallel. The inputs of each operation are searched for in a lookup table. Matches resulting in an exact or low error are removed from the floating point pipeline and used directly as output. Matches producing highly inaccurate results are computed on exact hardware to minimize application error. We simulate our design by placing ARGA within each core of an Nvidia Kepler Architecture Titan and an AMD Southern Island 7970. We show our design improves performance throughput by up to 2.7× and improves EDP by 5.3× for 6 GPGPU applications while maintaining less than 5% output error. We also show ARGA accelerates inference of a LeNet NN by 2.1× and improves EDP by 3.7× without significantly impacting classification accuracy. Daniel Peroni, Mohsen Imani, Hamid Nejatollahi, Nikil Dutt, Tajana Rosing |
DAC | 1 |
| 2018 | CANNA: Neural network acceleration using configurable approximation on GPGPUabstractNeural networks have been successfully used in many applications. Due to their computational complexity, it is difficult to implement them on embedded devices. Neural networks are inherently approximate and thus can be simplified. In this paper, CANNA proposes a gradual training approximation which adaptively sets the level of hardware approximation depending on the neural network's internal error, instead of apply uniform hardware approximation. To accelerate inference, CANNA's layer-based approximation approach selectively relaxes the computation in each layer of neural network, as a function its sensitivity to approximation. For hardware support, we use a configurable floating point unit in Hardware that dynamically identifies inputs which produce the largest approximation error and process them instead in precise mode. We evaluate the accuracy and efficiency of our design by integrating configurable FPUs into AMD's Southern Island GPU architecture. Our experimental evaluation shows that CANNA achieves up to 4.84× (7.13×) energy savings and 3.22× (4.64×) speedup when training four different neural network applications with 0% (2%) quality loss as compared to the implementation on baseline GPU. During the inference phase, our layer-based approach improves the energy efficiency by 4.42× (6.06×) and results in 2.96× (3.98×) speedup while ensuring 0% (2%) quality loss. Mohsen Imani, Max Masich, Daniel Peroni, Pushen Wang, Tajana Rosing |
ASP-DAC | 3 |
| 2017 | CFPU: Configurable Floating Point Multiplier for Energy-Efficient ComputingabstractMany applications, such as machine learning and data sensing are statistical in nature and can tolerate some level of inaccuracy in their computation. Approximate computation is a viable method to save energy and increase performance by trading energy for accuracy. There are a number of proposed approximate solutions, however, they are limited to a small range of applications because they cannot control the error rate of their output. In this paper, we propose a novel approximate floating point multiplier, called CFPU, which significantly reduces energy and improves performance of multiplication at the expense of accuracy. Our design approximately models multiplication by replacing the most costly step of the operation with a lower energy alternative. In order to tune the level of approximation, CFPU dynamically identifies the inputs which will produce the largest approximation error and processes them in precise CFPU mode. We showed that our CFPU can outperforms a standard FPU when at least 4% of multiplications are performed in approximate mode. In our tested applications this percentage of multiplications is substantially higher, leading to significant energy savings. Our experimental evaluation on AMD Southern Island GPU shows that replacing the proposed CFPU with traditional FPUs results in 77% energy savings and 3.5x energy-delay product improvement over eight general OpenCL applications while providing acceptable quality of service. In addition, for the same level of accuracy, the CFPU provides 2.4x energy-delay product improvement compared to state-of-the-art approximate multipliers. Mohsen Imani, Daniel Peroni, Tajana Rosing |
DAC | 2 |
| 2017 | Efficient neural network acceleration on GPGPU using content addressable memoryabstractRecently, neural networks have been demonstrated to be effective models for image processing, video segmentation, speech recognition, computer vision and gaming. However, high energy computation and low performance are the primary bottlenecks of running the neural networks. In this paper, we propose an energy/performance-efficient network acceleration technique on General Purpose GPU (GPGPU) architecture which utilizes specialized resistive nearest content addressable memory blocks, called NNCAM, by exploiting computation locality of the learning algorithms. NNCAM stores highly frequent patterns corresponding to neural network operations and searches for the most similar patterns to reuse the computation results. To improve NNCAM computation efficiency and accuracy, we proposed layer-based associative update and selective approximation techniques. The layer-based update improves data locality of NNCAM blocks by filling NNCAM values based on the frequent computation patterns of each neural network layer. To guarantee the appropriate level of computation accuracy while providing maximum energy saving, our design adaptively allocates the neural network operations to either NNCAM or GPGPU floating point units (FPUs). The selective approximation relaxes computation on neural network layers by considering the impact on accuracy. In evaluation, we integrate NNCAM blocks with the modern AMD southern Island GPU architecture. Our experimental evaluation shows that the enhanced GPGPU can result in 68% energy savings and 40% speedup running on four popular convolutional neural networks (CNN), ensuring acceptable < 2% quality loss. Mohsen Imani, Daniel Peroni, Yeseong Kim, Abbas Rahimi, Tajana Rosing |
DATE | 2 |