While the Fat-Tree network topology represents the dominant state-of-art solution for large-scale HPC networks, its scalability in terms of power, latency, complexity, and cost is significantly challenged by the ever-increasing communication bandwidth among tens of thousands of heterogeneous computing nodes. We propose 3D-Hyper-FleX-LION, a flat hybrid electronic-photonic interconnect network that leverages the multichannel nature of modern multi-terabit switch ASICs (with 100 Gb/s granularity) and a reconfigurable all-to-all photonic fabric called Flex-LIONS. Compared to a Fat-Tree network interconnecting the same number of nodes and with the same oversubscription ratio, the proposed 3D-Hyper-FleX-LION offers a 20% smaller diameter, 3x lower power consumption, 10X fewer cable connections, and 4x reduction in the number of transceivers. When bandwidth reconfiguration capabilities of Flex-LIONS are exploited for non-uniform traffic workloads, simulation results indicate that 3D-Hyper-FleX-LION can achieve up to 4x improvement in energy efficiency for synthetic traffic workloads with high locality compared to Fat-Tree.

Silicon Photonics (SiPs) can overcome the energy and bandwidth limitations of electrical interconnects in networks-on-chip (NoCs) and enable efficient global all-to-all connectivity-the ideal from a performance perspective. Unfortunately, state-of-the-art SiP switching fabrics impose power overheads for thermo-optical control of microring resonators (MRs), excessive crosstalk, or challenging physical layout. The Arrayed Waveguide Grating Router (AWGR) is a SiP device that provides layout-efficient and scalable all-to-all connectivity through wavelength-routing on a passive and compact platform. Recent technological advances now enable AWGR integration with significantly reduced footprint (2), crosstalk (<;-38dB), and loss (<;2dB), making AWGRs emerge as a major enabler for energy-efficient all-to-all connectivity in NoCs. This paper, for the first time, populates the design space of AWGR-based NoC topologies and compares AWGRs to state-of-the-art SiP fabrics and aggressive electrical baselines. Our results make a compelling case for AWGRs in interposer-based systems with processor disintegration, which have high bandwidth demands, large on-chip distances, and less stringent area constraints. AWGR-based NoCs can offer an average of 1.67× power savings, 1.23× speed-up, and 1.5× lower energy-delay-product (EDP) on PARSEC3.0/SPLASH-2× workloads compared to electrical baselines, and fewer waveguides, wavelengths, or MRs than alternative SiP crossbar fabrics.

Smaller feature size, lower supply voltage, and faster clock rates have made modern computer systems more susceptible to faults. Although previous fault tolerance techniques usually target a relatively low fault rate and consider error recovery less critical, with the advent of higher fault rates, recovery overhead is no longer negligible. In this paper, we propose a scheme that leverages and revises a set of compiler optimizations to design, for each application hotspot, a smart recovery plan that identifies the minimal set of instructions to be re-executed in different fault scenarios. Such fault scenario and recovery plan information is efficiently delivered to the processor for runtime fault recovery. The proposed optimizations are implemented in LLVM and GEM5. The results show that the proposed scheme can significantly reduce runtime recovery overhead by 72%.

Domain Wall Memory (DWM) with ultra-high density and comparable read/write latency to DRAM is an attractive replacement for CMOS-based devices. Unlike DRAM, DWM has non-uniform data access latency that is proportional to the number of shift operations. While previous works have demonstrated the feasibility of using DWM as main memory and have proposed different ways to alleviate the impact of shift operations, none of them have addressed the performance-critical metadata accesses, in particular page table accesses. To bridge this gap, this paper aims at accelerating page table walk in DWM-based main memory from two innovative aspects. First of all, we propose a new page table layout and leverage the positions of access ports in DWM to differentiate the state of page table entries. In addition, we propose a technique to pre-align the access ports to the positions to be accessed in the near future, thus hiding shift latency to the maximum extent. Since both address translation and context switching are affected by page table access latency, the proposed technique can effectively improve system performance and user experience.