Recently, there has been increasing interest in developing and deploying deep graph learning algorithms for various tasks, such as fraud detection and recommender systems. However, there is a limited number of publicly available graph-structured datasets, most of which are small compared with production-sized applications or limited in their application domain. In this work, we tackle this shortcoming by proposing a synthetic graph generation tool that enables scaling datasets to production-size graphs with trillions of edges and billions of nodes. The proposed method comprises a series of parametric models that can either be randomly initialized or fit to proprietary datasets. These models can then be released to researchers to study graph methods on the synthetic data, facilitating prototype development and novel applications. We demonstrate the generalizability of the framework across various datasets, mimicking their structural and feature distributions, as well as the ability to scale them to varying sizes, demonstrating their usefulness for benchmarking and model development. Code can be found on GitHub.

Customizing Convolution Neural Networks (CNN) for production use has been a challenging task for DL practitioners. This paper intends to expedite the model customization with a model hub that contains the optimized models tiered by their inference latency using Neural Architecture Search (NAS). To achieve this goal, we build a distributed NAS system to search on a novel search space that consists of prominent factors to impact latency and accuracy. Since we target GPU, we name the NAS optimized models as GPUNet, which establishes a new SOTA Pareto frontier in inference latency and accuracy. Within 1ms, GPUNet is 2x faster than EfficientNet-X and FBNetV3 with even better accuracy. We also validate GPUNet on detection tasks, and GPUNet consistently outperforms EfficientNet-X and FB-NetV3 on COCO detection tasks in both latency and accuracy. All of these data validate that our NAS system is effective and generic to handle different design tasks. With this NAS system, we expand GPUNet to cover a wide range of latency targets such that DL practitioners can deploy our models directly in different scenarios.

We present a k-bit encoding of the k-bit binary integers based on a discrete logarithm representation. The representation supports a discrete logarithm number system (DLS) that allows integer multiplication to be reduced to addition and integer exponentiation to be reduced to multiplication. We introduce right-to-left bit serial conversion, deconversion, and unified conversion/deconversion algorithms between binary and DLS. The conversion algorithms utilize O(k) additions, do not require the use of a multiplier, and are applicable at least up to 128-bit integers. We illustrate the use of the representation in determining a novel and efficient integer power modulo 2koperation |xy|2kand compare hardware performance with a current state-of-the-art method. Furthermore, we describe properties of the conversion mappings that allow compact table lookup structures to be employed for direct conversion to and deconversion from the DLS encoding. Our lookup architecture allows 16-bit conversion and deconversion mappings to be realized with table sizes of order 2-8 Kbytes, which is up to a 64\times size reduction of the 128 Kbytes of an arbitrary 16-bits-in, 16-bits-out function table. Performance and area results that demonstrate the effectiveness of the table lookup architecture are given. The lookup methodology extends to other 16-bit integer functions such as multiplicative inverse and squaring operations.

We describe several integer function properties which in combination allow direct lookup tables to be reduced in size and structure to simpler lookup trees. Our principal result is a novel table lookup method based on a mapping of a lookup tree to a row-by-column ROM with pre and post processing logic substantially reducing the table size. Our lookup architecture allows common 16-bit integer functions such as multiplicative inverse, square, and the discrete log to be realized with table size of order 2-8 Kbytes, in comparison to the 128 Kbyte size of an arbitrary 16-bits-in 16-bits-out function table. The lookup methodology is illustrated with specific development of the 16-bit integer discrete-log function. Implementation for both unnormalized and normalized indices are synthesized into standard cell netlists and performance and area results are given that demonstrate their effectiveness.

Summary form only given. The edge connectivity of a graph G = (V, E) is defined as the function, /spl lambda/: V /spl times/ V /spl rarr/ N, that associates to any pair of vertices (u, v) the maximum number of edge-disjoint paths connecting the two vertices, /spl lambda/(u, v). In this paper, we present a method for determining the function /spl lambda/(u,v) for all vertex pairs in a 4-regular graph which achieves O(|V|) running time (with a small constant factor) and O(|V|) space complexity. We show with our method that determination and traversal of an Eulerian tour of each component of the 4-regular graph along with appropriate bookkeeping is enough for determining /spl lambda/(u, v) for all pairs (u,v).

We introduce an inheritance property and related table lookup structures applicable to simplified evaluation of the modular operations "multiplicative inverse", "discrete log", and "exponential residue" in the particular modulus 2/sup k/. Regarding applications, we describe an integer representation system of Benschop for transforming integer multiplications into additions which benefits from our table lookup function evaluation procedures. We focus herein on the multiplicative inverse modulo 2/sup k/ to exhibit simplifications in hardware implementations realized from the inheritance property. A table lookup structure given by a bit string that can be interpreted with reference to a binary tree is described and analyzed. Using observed symmetries, the lookup structure size is reduced allowing a novel direct lookup process for multiplicative inverses for all 16-bit odd integers to be obtained from a table of size less than two KBytes. The 16-bit multiplicative inverse operation is also applicable for providing a seed inverse for obtaining 32/64-bit multiplicative inverses by one/two iterations of a known quadratic refinement algorithm.

SRAM-based field programmable gate arrays (FPGAs) have fixed numbers of wires, switches, and look-up tables. An application does not fully utilize all available components in a FPGA, e.g. wires. In this paper, we propose methods to improve reliability of less reliable operational interconnections by efficiently utilizing unused wires to mark errors dynamically. With these methods, we are able to improve the reliability of more than two-thirds of all interconnections in the studied MCNC benchmarks. As a result, the overall unreliability of operational interconnections decreases more than 20%.

We describe a high radix integer division algorithm where the divisor is prescaled and the quotient is postscaled without modifying the dividend to obtain an identity N=Q/sup *//spl times/D+R/sup */ with the quotient Q/sup */ differing from the desired integer quotient Q only in its lowest order high radix digit. Here the "oversized" partial remainder R/sup */ is bounded by the scaled divisor with at most one additional high radix digit selection needed to reduce the partial remainder and augment the quotient to obtain the desired integer division result N=Q/spl times/D+R with 0/spl les/R/spl les/D-1. We present a high radix multiplicative version of this algorithm where a k/spl times/p digit base /spl beta/ rectangular aspect ratio multiplier allows quotient digit selection in radix /spl beta//sup k-1/ with a cost of only one k/spl times/p digit multiply per high radix digit, plus the fixed pre- and post-scaling operation costs. We also present a Booth radix 4 additive version of this algorithm where appropriately compressed representation of the partial remainder with Booth digits {-2, -1, 0, 1, 2} allows successive quotient digit selection from the leading partial remainder digit without the iterative table lookups required in SRT division.

Many function approximation procedures can obtain enhanced accuracy by an efficient table lookup of a product z=f(x)g(y). Both x and y are represented by indices of i leading bits (typically 7<i<16) for arguments normalized to [0, 1] or [1, 2]. Direct bipartite lookup employs 1/2 bits each of x and y yielding roughly an 1/2 bit result which can lose 2 to 3 bits of accuracy when f and g are nonlinear. Indirect bipartite lookup first generates i/2 bit interval index values for f(x) and g(y) using separate j-bits-in 1/2bits-out tables for f(x) and g(y) where i/2<j