Shuang Liang 0012

dblp:20/1080-12 · DBLP profile ↗
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8ranked-venue papers
5as first author
6since 2021 · last 2026
0000-0003-0881-5549ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 4 first-author · 6 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021Artificial intelligence and machine learning · 1 · 1 first-author
YearPublicationVenuePosition
2026 Hardware-Efficient Union-Find Decoder Towards Scalable Topological Quantum Codes
Shuang Liang 0012, Jubo Xu, Yuncheng Lu, Hao Mark Chen, Hongxiang Fan
ASP-DAC1
2026 FastTTS: Accelerating Test-Time Scaling for Edge LLM Reasoning
Hao Mark Chen, Zhiwen Mo, Guanxi Lu, Shuang Liang 0012, Lingxiao Ma, Wayne Luk, Hongxiang Fan
ASPLOS (2)4
2026 Advancing Full-Stack Acceleration for SchröDinger-Style Quantum Simulation
abstract
Recent developments in quantum hardware, including the scaling of physical qubits and advanced quantum error correction techniques, have increased the number of reliable logical qubits. However, this progress has introduced new challenges for quantum algorithm developers. Limited access to physical quantum machines and the insufficient performance of classical quantum simulators for near-term scales ($\sim 30$logical qubits) hinder the simulation and validation of quantum algorithms. To address this urgent need for improving simulation performance, we propose a novel end-to-end full-stack solution for Schrödingerstyle simulation that jointly explores algorithm, software, and hardware optimizations. At the algorithmic level, by identifying the inefficiency in executing complex signed permutations and complex unitary permutation gates, we introduce index redirection and pre-compute merging that significantly reduce data movement and computational complexity. At the hardware level, we propose a reconfigurable dataflow architecture with adaptive memory scheduling and swapping optimizations. At the software level, an end-to-end toolchain is introduced to jointly explore both algorithmic and hardware optimizations. A comprehensive evaluation across a large suite of quantum circuits demonstrates that our work achieves a maximum speedup exceeding$50 \times$over the GPU-based Qiskit baseline.
Shuang Liang 0012, Yuncheng Lu, Ce Guo 0002, Paul H. J. Kelly, Wayne Luk, Hongxiang Fan
HPCA1
2026 Coset Ensemble Decoder for Quantum Error Correction with Algorithm-Hardware Co-Design
Shuang Liang 0012, Jubo Xu, Giulio Bassanino, Qianzhou Wang, Yuncheng Lu, Zhiwen Mo, Paul H. J. Kelly, Wayne Luk, Hongxiang Fan
ISCA1
2025 Versatile Cross-platform Compilation Toolchain for Schrödinger-style Quantum Circuit Simulation
abstract
While existing quantum hardware resources have limited availability and reliability, there is a growing demand for exploring and verifying quantum algorithms. Efficient classical simulators for high-performance quantum simulation are critical to meeting this demand. However, due to the vastly varied characteristics of classical hardware, implementing hardware-specific optimizations for different hardware platforms is challenging. To address such needs, we propose CAST (Cross-platform Adaptive Schrödinger-style Simulation Toolchain), a novel compilation toolchain with cross-platform (CPU and Nvidia GPU) optimization and high-performance backend supports. CAST exploits a novel sparsity-aware gate fusion algorithm that automatically selects the best fusion strategy and backend configuration for targeted hardware platforms. CAST also aims to offer versatile and high-performance backend for different hardware platforms. To this end, CAST provides an LLVM IR-based vectorization optimization for various CPU architectures and instruction sets, and a PTX-based code generator for Nvidia GPU support. We benchmark CAST against IBM Qiskit, Google QSimCirq, Nvidia cuQuantum backend, and other high-performance simulators. On various 32-qubit CPU-based benchmarks, CAST achieves up to 8.03x speedup than Qiskit. On various 30-qubit GPU-based benchmarks, CAST achieves up to 39.3x speedup than Nvidia cuQuantum backend.
Yuncheng Lu, Shuang Liang 0012, Hongxiang Fan, Ce Guo 0002, Wayne Luk, Paul H. J. Kelly
DAC2
2024 PCQ: Parallel Compact Quantum Circuit Simulation
abstract
Since quantum computers are not readily available, much quantum computing research such as quantum algorithm verification has to be conducted on classical computer platforms. While many quantum circuit simulators have been developed on CPUs and GPUs, the potential of FPGAs as a platform with parallel computing capabilities and high energy efficiency has not been fully explored. This paper describes a novel approach with two modes of data movement optimization for an FPGA-based parallel pipelined dataflow architecture targeting a compact computation format. A data decoupling method is adapted to partition computing tasks and data into non-interacting sub- sets, significantly reducing external data interaction overhead. The proposed approach shows significant promise in improving performance and energy efficiency compared with existing state vector based CPU, GPU, and FPGA implementations.
Shuang Liang 0012, Yuncheng Lu, Ce Guo 0002, Wayne Luk, Paul H. J. Kelly
FCCM1
2018 FP-BNN: Binarized neural network on FPGA
Shuang Liang 0012, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei
Neurocomputing1
2016 Relation-oriented resource allocation for multi-accelerator systems
abstract
This paper presents a novel approach for allocating resources in systems with multiple accelerators. It has three main contributions. First, a new model based on Birkhoff's representation theory in capturing the ordering properties of resource allocation requests (RArs). Second, an effective technique for resource allocation based on this model, targeting systems with multiple accelerators. Third, the evaluation of the proposed approach for Maxeler MPC-X multi-accelerator systems, demonstrating time-efficiency and 30%-50% failure-rate decrease (FRD) on random input dataset.
Mark Stillwell, José Gabriel F. Coutinho, Wenlai Zhao, Shuang Liang 0012, Wayne Luk, Alexander L. Wolf, Yuchun Ma
ASAP6