Demo Data from EDBT 2026 / reviewers in the wild / expert
Huey Ling
dblp:20/1281
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1970
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 50% Processor architecture and microarchitecture · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › computer arithmetic
binary multiplication |
0.0 | 1 | 1970 | High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm · IEEE Trans. Computers 1970 |
Integrated circuit design
digital arithmetic circuits |
0.0 | 1 | 1970 | High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm · IEEE Trans. Computers 1970 |
Methods — techniques the papers use, named apart from their topics
block decoding · 0.0add-and-shift · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1970 | High-Speed Computer Multiplication Using a Multiple-Bit Decoding AlgorithmabstractThis paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion. Huey Ling |
IEEE Trans. Computers | 1 |