During the last years, natural water resources like ponds, lakes, and rivers have faced a significant threat due to mismanagement of activities like the discharge of untreated industrial effluents, sewage water, wastes, etc. Water plays an essential role in all aspects of our lives. Therefore, detecting water pollutants causing contamination is imperative to sustain the quality of life. Therefore, it became mandatory to examine water quality to ensure that only safe water is available for us and other biological life. Thus, accurate sensors have become increasingly necessary, providing precise and coherent data, particularly when measuring sensitive natural sources. However, false readings due to poor quality measurements and individual impact related to the sensors can cause false conclusions. As a result, the information has a detrimental influence on making appropriate decisions. Our research aims to compare and analyze sensors based on two statistics metrics: the Relation Error and Information Gain, using the water quality standards provided by World Health Organization (WHO) as a guideline. pH, Dissolved Oxygen (DO), Electric Conductivity (EC), Turbidity, and Temperature are the measured parameters in this research. Next, to determine the actual state of the analyzed water source, we have developed a water quality indexation and classification based on the National Sanitation Foundation Water Quality (NSFWQI) method.

Triboelectric harvesters do not have to prove their potential anymore. Nevertheless, those harvesters’ structural and functional characteristics must be optimized to produce sufficient energy to power commonly used embedded systems. The most performant generators use nanotechnology (TENG). However, as recent research shows, optimization depends on the application. The force, frequency, and velocity, for example, are all variables that will affect the optimal structure. The analysis presented in this work gives a better understanding of the different factors to consider to finetune triboelectric acoustic-energy harvesters. Since sound carries little energy, particular attention must be put to the membrane structure to produce sufficient energy for self-powering. The harvester consists of two dielectric layers and two electrodes. We focus on the optimal production technique for those dielectrics (negative and positive). First, the fundamentals and different structural methods to increase performance are discussed. Then, the production of the subsequent negative dielectric is studied. The films were characterized by X-ray powder diffraction (XRD) and Field emission scanning electron microscopy (FESEM). The results indicated that better uniformity was achieved using the spin-coating method.

Embedded Artificial Intelligence (AI) and the use of deep neural networks on embedded devices is becoming increasingly popular. The rise in popularity comes from the advantages gained from executing inference locally, such as privacy, and the increase in available platforms to accelerate AI. An example of such platforms are Field Programmable Gate Arrays (FPGAs). The flexibility of FPGAs resulted in the development of several accelerators for AI. One of these tools that is gaining more and more interest is Xilinx Vitis AI, which uses a configurable Deep Processing Unit (DPU) in an FPGA. The DPU is not only scalable in resource consumption, but also the frequency at which it operates. In this paper, the influence on the power and energy consumption of the DPU is investigated for different DPU configurations and frequencies. As a result, it is shown that increasing the frequency of the DPU can compensate a reduction in resource consumption. Furthermore, an increase in resources and frequency can result in an overall lower energy consumption due to a higher power consumption for a shorter time.

Motivated by an increasing interest from startups in embedded Artificial Intelligence (AI) and by their limited expertise, the AITIA Project targets the development of embedded AI techniques for industrial applications. This extended abstract presents the motivation and the solutions being developed towards four use cases: smart sensors, network intrusion detection, driver-assistance systems, and Industry 4.0.

Summary Consider the situation of a patient carrying a body area network with sensors measuring different body characteristics. These data should be securely sent to the cloud and only retrievable by doctors authorized by the patient. Even the cloud service provider should not be able to derive the sensible data. In order to address this problem, this paper first proposes a highly efficient certificate‐based signcryption scheme, able to execute signing and encryption in one single phase and to guarantee the link between identity and public key. We show that our proposed scheme outperforms others both in computation and communication complexity. Next, based on this primitive, a complete proxy re‐signcryption scheme is presented to be integrated in this smart body area network. The proposed schemes are based on elliptic curve operations and do not use compute intensive pairing operations, like previous proposals. We show that our scheme outperforms previous proposed proxy re‐signcryption schemes in the literature.

Recently, fabrication laboratories (Fab Labs) have been shown to have a great impact on learners' academic and personal progress. As a result, an increasing effort is being put to integrate Fab Labs into schools' curricula. Yet, owing to the high cost of setting up and maintaining Fab Labs as well as the lack of sufficient funding for most schools and universities, only a limited number of institutions can afford them. In this article, we propose a new concept called Fabrication-as-a-Service (FaaS) that uses Internet of Things to democratize access to Fab Labs via enabling a wide learning community to remotely access these computer-controlled tools and equipment over the Internet. It employs a two-tier architecture consisting of a hub, deployed in the cloud, and a network of distributed Fab Labs. Each Fab Lab interacts with the hub and other digital labs via a Fab Lab Gateway. This is to support scalability and high availability of fabrication services as well as ensure the system's security. FaaS also adopts an innovative master-slave approach that uses inexpensive external hardware to monitor and control the activity of expensive fabrication equipment. This article also describes the FaaS deployment in the context of the European Union Horizon 2020 NEWTON project. Multiple scenarios have been deployed to fully illustrate the benefits of the FaaS architecture and to assess the performance of its communication protocol stack.

The relatively low-cost of the Micro-Electromechanical Systems (MEMS) microphones together with recent advances in the MEMS technology facilitates the construction of large MEMS microphone arrays, which are used to collect the acoustic information from certain beamed directions by applying beamforming techniques. The use of beamforming techniques to steer the microphone array response is the principle used by acoustic cameras to graphically display the acoustic information in a heatmap form. Our demonstrator exploits the heterogeneous nature of System-on-Chip (SoC) FPGA systems by generating real-time acoustic images on the FPGA component while alleviating the Wireless Sensor Networks (WSN) bandwidth limitations by performing acoustic image processing locally on the hard-core processor. As a result, a real-time acoustic heatmap is generated, enabling the visualization of the sound sources characteristics.

Summary Cloud computing offers a simple way to provide access to servers, storage, databases, and a broad set of application services over the Internet. Its popularity is growing spectacularly. Consequently, there is a need for strong authentication schemes, offering besides data privacy also identity privacy during these actions. Therefore, this paper presents 2 user‐friendly protocols, called the autonomous, anonymous, and authentication—AAA1 and AAA2—schemes, able to derive the required security material at user's side without the need of a secure channel between user and registration center. The protocol AAA2 has the added functionality to guarantee unforgeability and non‐repudiation of the request. Only simple elliptic curve operations, together with hashes and symmetric key encryptions are used. The proposed protocols are 2‐factor based, requiring the knowledge of the password and the possession of a correctly installed smartphone, and are very efficient to be executed on the smartphone because of a small amount of computations. As an application, we show how AAA1 can be utilized in a communication protocol for monitoring and AAA2 for charging and discharging of electrical vehicles with the smart grid. Moreover, these proposed solutions allow a much better performance, compared with the state of the art protocols in this field.

In this paper, we describe the architecture of a collaborative and real‐time environment for remote experiments. We also introduce a web‐based remote lab composer, which allows the interconnection and exchange of data between remote laboratories. The environment is created with web standards as HTML5 such that no plug‐in needs to be installed by the user. Users are able to use the remote lab simultaneously and in collaboration. This collaboration between users is made feasible by adopting a message broker. We will discuss how Google Coder is used to develop, change, or create a user interface for a remote experiment and how the labs can be shared in the cloud. Our newest addition to this research consists of a drag and drop lab composer, which allows Lab‐developers to use standard widgets, data‐visualization tools, and data‐ports to compose complex remote labs. A lab‐composer engine is developed to automate the coupling of the physical instances and collect the data to be visualized. The principles behind our lab‐composer engine are explained in the last part of the paper.

Nowadays, microphone arrays are used in many applications for sound-source localization or acoustic enhancement. The current Micro-Electro-Mechanical Systems (MEMS) technology allows the development of networks of microphone arrays at a relatively low cost. Unfortunately, the evaluation of these networks requires controlled acoustic environments, such as anechoic chambers, to avoid possible distortions and acoustic artifacts. In this paper, we present a partial reconfigurable FPGA platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network's topology or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. In addition, our platform is also capable to converge to the ideal network with regards to power consumption, while still maintaining the desired level of sound-source localization accuracy. A graphical user interface provides a friendly control of the network and the parameters under test during the execution of the partial reconfiguration operations. Several experiments are presented to demonstrate some of the capabilities of our platform.

The current Micro-Electro-Mechanical System (MEMS) technology allows to deploy relatively low-cost Wireless Sensor Networks (WSN) composed of MEMS microphone arrays for accurate sound-source localization. However, the evaluation and the selection of the most accurate and power-efficient network's topology is not trivial when considering dynamic MEMS microphone arrays. Despite software simulators are usually considered, they are high-computational intensive tasks which require hours to days to be completed. Our demonstrator is an FPGA-based network emulator, which provides a fast network design-space exploration. The user can easily evaluate a network's topology with different nodes' configurations and multiple sound sources in matter of seconds. An intuitive graphical user interface hides from the user the dynamic partial reconfigurations needed by the network emulator to set the node's configurations. As a result, a probability map generated from the fusion of the output data from the nodes and an error on the estimation of the sound-source location are graphically represented.

Sound-source localization is used in many different real-time acoustic applications. Microphone arrays have the potential capability to recognize, profile and locate sound-sources in noisy environments. The quality response of such sensor arrays, however, is determined by the quantity of microphones. A higher number of microphones increases the computational demand, making real-time response challenging. In this paper, we present a scalable and runtime reconfigurable architecture to provide accurate sound-source localization in real-time. On one hand, the reconfigurable architecture is designed to be scalable in order to support a variable number of microphones. On the other hand, we use runtime reconfigurable look-up tables (CFGLUTs) to provide a dynamic response in real-time. Experiments demonstrate how an accurate sound-source localization is obtained in less than a few hundred milliseconds. As far as we are aware, it is the first time that runtime reconfiguration is applied to a reconfigurable architecture consisting of a sensor array.

Microphone arrays are able to recognize, profile and locate sound-sources in noisy environments, but their quality is determined by the number of microphones. A higher number of microphones increases the computational demand, making real-time response challenging. In this demo, we present a scalable and runtime reconfigurable architecture able to support a variable number of microphones and orientations in order to provide accurate sound-source localization in real-time.

Low-power, high-performance computing nowadays relies on accelerator cards to speed up the calculations. Combining the power of GPUs with the flexibility of FPGAs enlarges the scope of problems that can be accelerated [2, 3]. We describe the performance analysis of a desktop equipped with a GPU Tesla 2050 and an FPGA Virtex-6 LX240T. First, the balance between the I/O and the raw peak performance is depicted using the roofline model [4]. Next, the performance of a number of image processing algorithms is measured and the results are mapped onto the roofline graph. This allows to compare the GPU and the FPGA and also to optimize the algorithms for both accelerators. A programming toolchain is implemented, consisting of OpenCL for the GPU and several High-Level Synthesis compilers for the FPGA. Our results show that the HLS compilers outperform handwritten code and offer a performance comparable to the GPU. In addition the FPGA compilers reduce the development time by an order of magnitude, at the expense of an increased resource consumption. The roofline model also shows that both accelerators are equally limited by the input/output bandwidth to the host. A well-tuned accelerator-based codesign, identifying the parallelism, the computation and data patterns of different classes of algorithms, will enable to maximize the performance of the combined GPU/FPGA system [1].

In this manuscript, we have explored how the use of DSP blocks in the implementation of two authenticated-encryption modes of AES can optimize the PAR figures. Our results reflect that a 20.98 % reduction in slice utilization can be achieved at a throughput higher than 25 Mbps (12 MHz) in the Artix-7 XC7A200TL FPGA.

Nowadays, processors alone cannot deliver what computation hungry image processing applications demand. An alternative is to use hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs). Applications, however, exhibit different performance characteristics depending on the accelerator. This paper describes the hybrid platform and the programming environment that allows to efficiently create programs on a combined GPU/FPGA desktop. We use the roofline model to identify the most appropriate accelerator for each application and High-Level Synthesis (HLS) tools to reduce the FPGA development time. To introduce our platform and tool chain both accelerators are compared by implementing a basic image operation. Next, a promising algorithm is explored and implemented, splitting and distributing the work between GPU, FPGA and CPU in order to validate the hybrid concept. Our results show that their combination exhibits a higher performance for computational intensive image processing applications than a GPU only.

Field programmable gate arrays (FPGAs) are generally used in sensor networks for accelerating complex algorithms, either at node or gateway level. The apparition of FPGAs in the market equipped with special blocks for performing logic operations at high-speed and reduced utilization of the platform fabric, allows the implementation of a number of algorithms mainly based on these embedded resources. In this manuscript, we have focused on the Xilinx Artix-7 platform. We have evaluated how replacing logic functions in the implementation of GF(2m) arithmetics and lightweight block ciphers can reduce the area and, consequently, the cost of the platform. Moreover, we provide an update of an IEEE 802.15.4 accelerator extended with key negotiation capabilities described in previous work. Our results suggest that FPGAs can be employed for developing infrastructure for Wireless Medical Sensor Networks (WMSNs) in cases where encrypting and authenticating a large stream of sensed data is required. In that case, traditional sensor nodes, typically based on microcontrollers and clocked at low frequencies can be ill-suited for real-time applications. Moreover, the fact that large intervals of time are required for executing both encryption and authentication schemes can impact the battery lifetime of the node in comparison of utilizing a separate coprocessor (e.g. based on FPGA) that can be turned on and off when required. Finally, promising results in terms of cost and power consumption are expected when the smallest platforms of the Artix-7 series are available.

In the Intelligent Distributed Environmental Assessment (IDEA) [3] system, sensors are used to measure noise and air pollution. The architecture is service-oriented, allowing application architects to combine services provided by the system platform in order to satisfy application needs. A typical user application may require a set of those services. Because of the sensor nodes' resource limitation, some services may not keep Quality of Service (QoS) levels stable over a long period, which could lead to Service Layer Agreement (SLA) violations. To maintain SLA, QoS levels must be estimated so that services can be properly invoked and combined to satisfy the user's QoS requirements. This paper proposes a novel approach to estimate QoS levels of web services. On the basis of monitored values of QoS parameters, a Naïve Bayes estimation model is developed to select the best-suited services. This paper also presents approaches adopted to monitor QoS levels of web services in the IDEA environment.

We developed a learning platform that integrates three different existing methods for virtual experiments in the context of electronics and electrics. These methods include the Falstad simulator, a webservice based on the de facto SPICE simulator in electronics, and an attractive 3D visualization model called Videomodels. Based on this platform, we evaluated the representation and perception of each method. The main conclusion that could be drawn from our study was that the simple self-explaining interactive technique, obtained by the Falstad simulator, will be the perfect model in a self-study environment. On the other hand, the attractive three dimensional representation of the Videomodels, turns out to play a very important role in motivating the students during the lessons.

This paper proposes an FPGA-based application-specific elliptic curve processor over a prime field. This research targets applications for which compactness is more important than speed. To obtain a small datapath, the FPGA's dedicated multipliers and carry-chain logic are used and no parallellism is introduced. A small control unit is obtained by following a microcode approach, in which the instructions are stored in the FPGA's Block RAM. The use of algorithms that prevent Simple Power Analysis (SPA) attacks creates an extra cost in latency. Nevertheless, the created processor is flexible in the sense that it can handle all finite field operations over 256-bit prime fields and all elliptic curves of a specified form. The comparison with other implementations on the same generation of FPGAs learns that our design occupies the smallest area.

This survey paper proposes an overview of contemporary FPGA-related technologies and techniques that can be used for data and system security. As such we will give an overview of the currently available features in commonly used FPGAs and link these features to established security techniques. The main goal is to evaluate the pros and contras of the different techniques and technologies in order to give directions on the security strategy.