As minimum feature size and pitch spacing further decrease in advanced technology nodes, many new design constraints and challenges are introduced, such as regularity, middle of line (MOL) structures, and pin-access challenges. In this work, we propose a comprehensive study on standard cell layout regularity and pin access optimization. Given irregular cell layout from old technology nodes, our cell optimization tool can search unidirectional migrated result where the self-aligned double patterning (SADP) and MOL based design constraints are satisfied, and the pin-accessibility is optimized. This problem is formulated as a general integer linear programming (ILP), which may suffer from long runtime for some large standard cell cases. Therefore, we also develop a set of hybrid techniques to quickly search for high-quality solutions. The experimental results demonstrate the effectiveness of our approaches.

As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), manufacturability challenges are exacerbated. The nanopatterning through the 193nm lithography is being pushed to its limit, through double/triple or more general multiple patterning, while non-conventional lithography technologies such as extreme ultra-violet (EUV), e-beam direct-write (EBDW), and so on, still have grand challenges to be solved for their adoption into IC volume production. This tutorial will provide an overview of key overarching issues in nanometer IC design for manufacturability (DFM) with these emerging lithography technologies, from modeling, mask synthesis, to physical design and beyond.

A spacer-type self-aligned double pattering (SADP) is a pitch-splitting sidewall image method that is a major option for sub-30nm device node manufacturing due to its lower overlay sensitivity and better process window compared to other double patterning processes, such as litho-etch-litho-etch (LELE). SADP is in production use for 1D patterns in NAND Flash memory applications but applying SADP to 2D random logic patterns is challenging. In this paper, we describe the first layout decomposition methods of SADP lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two mask approach using a core (mandrel) mask and a trim mask. This paper describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. We evaluate our technique on 22nm node industrial standard cells and logic designs. Experimental results show that our proposed layout decomposition for SADP effectively decomposes many challenging 2D layouts.

Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious device performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the lithographic aerial image fidelity and neighboring geometric proximity. With our new LER model, we perform robust LER aware poly layout optimization to minimize the degradation of device performance, in particular leakage current. The results on 32nm node standard cells show average 91.26% reduction of leakage current and 4.46% improvement of saturation current at the worst case despite 8.86% area penalty.

The printed image of a layout that satisfies the double patterning lithograph (DPL) constraints may not have good fidelity if the layout neglects optical proximity correction (OPC). Simultaneously considering DPL and OPC becomes necessary when gene rating layouts, especially in routing stage. Moreover, one decomposed design with balanced mask density has a lower edge placement error (EPE)than an unbalance done[6]. This work proposes a compre-hensive conflict graph (CCG)to enable detailed routers to simultaneously consider DPL, OPC, and mask density to gene rate litho-friendly layouts. This work then develops an DPL-aware and OPC-friendly gridless detailed routing (DOPPLER) by applying CCG in a gridless routing model. A density variation threshold annealing-based routing flow is also proposed to prevent DOPPLER from falling into a sub-optimal mask density balance. Compared with existing DPL-aware detailed routing works, DOPPLER demon-stratesanaverage 73.84% of EPE hotspot reduction with a satisfactory mask density at the cost of an average increase of 0.08% wire-length, 15.14% number of stitches, and 77.28% runtime.

In this paper we propose a new equivalent contact resistance model which accurately calculates contact resistances from contact area, contact position, and contact shape. Based on the impact of contact resistance on the saturation current, we perform robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty. The results on industrial 32nm node standard cells show up to 3.45% delay improvement under nominal process condition, 86.81% reduction in the delay variations between the fastest and slowest process corners.

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. In this paper we propose a comprehensive sensitivity metric which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations. We develop first-order models to compute these sensitivities, and perform robust layout optimization by minimizing the total delay sensitivity to reduce the delay variation on the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners to reduce the leakage current on the process corner. The results on industrial 45nm node standard cells show up to 76% improvement in non-rectangular delay variation under nominal process condition, 24% reduction in the delay difference between the fastest and slowest process corners, and up to 90% reduction in leakage current at the fastest process corner.

In this paper, we present an efficient lithography aware detailed (ELIAD) router to enhance silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first quantitatively show that a pre-OPC litho-metric is highly uncorrelated with a post-OPC metric, which stresses the importance of a post-OPC litho-metric for design-time optimization. We then propose a compact post-OPC litho-metric for a detailed router (DR) based on statistical characterization, where the interferences among predefined litho-prone shapes are captured as a lookup table. Our litho-metric derived from the characterization shows high fidelity to the total edge placement error (EPE) in large scale, compared with Calibre OPC/optical rule check. Therefore, ELIAD powered by the proposed litho-metric can enhance the overall post-OPC printed silicon image. Experimental results on 65-nm industrial circuits show that ELIAD outperforms a rip-up/rerouting approach such as Resolution-enhancement-technique-Aware Detailed Routing with 8times more EPE hot spot reduction and 12times speedup. Moreover, compared with a conventional DR, ELIAD is only about 50% slower.

In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first propose a compact post-OPC litho-metric for a detailed router based on statistical characterization. We characterize the interferences among weak grids filled with one of predefined litho-prone shapes (e.g., jog-corner, via, line-end). Our litho-metric derived from the characterization shows high fidelity to total edge placement error (EPE) in large scale, compared with Calibre-OPC/ORC. As a chip itself is in the largest scale, ELIAD powered by the proposed metric can enhance the overall post-OPC printed silicon image. Experimental results on 65nm industrial circuits show that ELIAD outperforms a ripup/rerouting approach such as RADAR [17] with 8x more EPE hotspot reduction and 12x speedup. Also, compared with a conventional detailed router, ELIAD is only about 50% slower.

Double patterning technology (DPT) is a most likely lithography solution for 32/22nm technology nodes as of 2008 due to the delay of Extreme Ultra Violet lithography. However, it should hurdle two challenges before being introduced to mass production, layout decomposition and overlay error. In this paper, we present the first detailed routing algorithm for DPT to improve layout decomposability and robustness against overlay error, by minimizing indecomposable wirelength and the number of stitches. Experimental results show that the proposed approach improves the quality of layout significantly in terms of decomposability and the number of stitches with 3.6x speedup, compared with a current industrial DPT design flow.