Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope (SSavg), off current (IOFF), and on current (ION) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope.

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

Tunnel FET (TFET) is recognized to be one of the most promising candidates for ultra-low power applications due to its ultra-low off current and high compatibility with CMOS process. However, different from the typical features of MOSFET, some electrical characteristics of TFETs caused by asymmetric device structure and special conduction mechanism may make conventional topologies of circuits no longer applicable. In this paper, it is found that the TFETs stacking will result in severe current degradation behavior, which makes traditional topologies of logic gates may be not applicable. To solve this problem, a set of novel hybrid TFET-MOSFET topologies for standard logic cells are proposed. The proposed designs achieve more than 2 times lower hardware cost and intrinsic delay, and realize up to 4 times lower area-power-delay product (APDP) than that of conventional TFET-based logic circuits. Moreover, the proposed topologies can achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP than that of conventional MOSFET-based logic circuits. The proposed standard logic cells show great superiority for power-constraint applications.

In this paper, the minimum operation voltage (Vmin) shifts of static random access memory (SRAM) induced by random telegraph noises (RTN) are extracted from accurate transient simulation results, including the impacts of both strong and weak coupling RTNs. The turning point observed in the relation between the SRAM bitcell Vmin shift and RTN amplitude is explained with the help of the newly-defined discrepancy. Based on the extracted statistical failure probabilities in all bitcells, a new prediction method for RTN induced Vmin shift of SRAM array is proposed, including the interaction with process variation, which indicates that the Vmin shift is actually underestimated by traditional expectation. In addition, the RTN and process variation are found to be the dominate influence factors on Vmin shift under lower and higher VDD, respectively. The results provide accurate evaluation on the impacts of RTN and process variation on SRAM and are helpful for robust SRAM design in nanoscale technology.

In this paper, an industry-level new-generation EDA solution for reliability-aware design in nanoscale FinFET technology is presented for the first time, with new compact transistor aging models and upgraded circuit reliability simulator. Our work solves various issues found in FinFET silicon data of NBTI aging. Especially, instead of ignoring or less accurate NBTI recovery effect model in traditional simulators, accurate NBTI degradation and recovery models are proposed and validated by silicon data for full stress/recovery range in the FinFET technology. The history effect, one of the important features of NBTI which is missing in the existing industrial tools, is included based on new simulation methodology. Since FinFET reliability data suggests the conventional linear extrapolation method is no longer valid, an accurate fast-speed long-term prediction method is proposed based on smart iteration flows of equivalence. The frequency dependence of NBTI, which draws much attention, is included in the new simulator automatically. This work has been integrated into Cadence reliability simulator, providing designers an opportunity for accurate reliability-aware circuit design.

The organic resistance memories show great potentials for future flexible applications. In this paper the main challenges and typical recent progress of the organic resistance memory devices are discussed. A kind of single-component polymer resistance memory device based on polychloro-paraxylylene (parylene-C) is focused, with excellent chemical stability and high CMOS process compatibility as well as further reduction of operation current, which is promising for future information storage in flexible systems.