Demo Data from EDBT 2026 / reviewers in the wild / expert
Joachim Mucha
dblp:20/1584
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1981
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 93% Integrated circuit design · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.0 | 1 | 1981 | A Hardware Approach to Self-Testing of Large Programmable Logic Arrays · IEEE Trans. Computers 1981 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1981 | A Hardware Approach to Self-Testing of Large Programmable Logic Arrays · IEEE Trans. Computers 1981 |
Electronic design automation › hardware verification and test › VLSI testing
programmable logic array testing |
0.0 | 1 | 1981 | A Hardware Approach to Self-Testing of Large Programmable Logic Arrays · IEEE Trans. Computers 1981 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1981 | A Hardware Approach to Self-Testing of Large Programmable Logic Arrays · IEEE Trans. Computers 1981 |
Integrated circuit design › large-scale integration
VLSI circuits |
0.0 | 1 | 1981 | A Hardware Approach to Self-Testing of Large Programmable Logic Arrays · IEEE Trans. Computers 1981 |
Methods — techniques the papers use, named apart from their topics
nonlinear feedback shift register · 0.0circuit partitioning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1981 | Hardware Test Pattern Generation for Built-In Testing
Wilfried Daehn, Joachim Mucha |
ITC | 2 |
| 1981 | A Hardware Approach to Self-Testing of Large Programmable Logic ArraysabstractA hardware technique for testing large programmable arrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allows the testing of a PLA within a number of cycles that is a linear function of the number of inputs and product terms. A 8 X 16 X 8 PLA is completely tested within 52 cycles; a 16 X 48 X 8 PLA requires 132 cycles. The test patterns do not depend on the individual personalization of any PLA. So there is no more need of an extensive fault simulation or test pattern computation. The result is a fast efficient built-in test for PLA-macros, the most promising building blocks of VLSI circuits. Wilfried Daehn, Joachim Mucha |
IEEE Trans. Computers | 2 |