Demo Data from EDBT 2026 / reviewers in the wild / expert
Nicholas Y. Pang
dblp:20/1597
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1986
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › latency hiding
decoupled architecture |
0.0 | 1 | 1986 | A Simulation Study of Decoupled Architecture Computers · IEEE Trans. Computers 1986 |
Processor architecture and microarchitecture
instruction-level parallelism |
0.0 | 1 | 1986 | A Simulation Study of Decoupled Architecture Computers · IEEE Trans. Computers 1986 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1986 | A Simulation Study of Decoupled Architecture ComputersabstractDecoupled architectures achieve high scalar performance by cleanly splitting instruction processing into memory access and execution tasks. Several decoupled architectures have been proposed, and they all have two characteristics in common: 1) they have two separate sets of instructions, one for accessing memory and one for performing function execution. 2) The memory accessing task and the execution task communicate via architectural queues. James E. Smith 0001, Shlomo Weiss, Nicholas Y. Pang |
IEEE Trans. Computers | 3 |