EDBT 2026 Demo / reviewers in the wild / expert
Dan Zuras
dblp:20/169
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1Theory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
1 paper |
Algorithms and data structures · 77% Computational complexity · 23% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 77% High-performance computing · 12% Performance modeling and evaluation · 11% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Algorithms and data structures › number-theoretic algorithms
integer arithmetic |
0.0 | 1 | 1994 | More On Squaring and Multiplying Large Integers · IEEE Trans. Computers 1994 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 2 | 1988 | Integer Multiplication and Division on the HP Precision Architecture · IEEE Trans. Computers 1988 Integer Multiplication and Division on the HP Precision Architecture · ASPLOS 1987 |
Computational complexity
algebraic complexity |
0.0 | 1 | 1994 | More On Squaring and Multiplying Large Integers · IEEE Trans. Computers 1994 |
High-performance computing
performance optimization |
0.0 | 1 | 1988 | Integer Multiplication and Division on the HP Precision Architecture · IEEE Trans. Computers 1988 |
Methods — techniques the papers use, named apart from their topics
FFT multiplication · 0.0frequency analysis · 0.0instruction scheduling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | More On Squaring and Multiplying Large IntegersabstractMethods of squaring and multiplying large integers are discussed. The obvious O(n/sup 2/) methods turn out to be best for small numbers. Existing O(n/sup log/ /sup 3/log/ /sup 2/)/spl ap/O(n/sup 1.585/) methods become better as the numbers get bigger. New methods that are O(/sup log5/log/ /sup 3/)/spl ap/0(n/sup 1.465/), O(n/sup log/ /sup 7/log/ /sup 4/)/spl ap/O(n/sup 1.404/), and O(n/sup log/ /sup 9/log/ /sup 5/)/spl ap/O(n/sup 1.365/) presented. In actual experiments, all of these methods turn out to be faster than FFT multipliers for numbers that can be quite large (>37,000,000 bits). Squaring seems to be fundamentally faster than multiplying but it is shown that T/sub multiplyspl les/2T/sub square/+O(n).> Dan Zuras |
IEEE Trans. Computers | 1 |
| 1993 | On squaring and multiplying large integersabstractMethods of squaring large integers are discussed. The obvious O(n/sup 2/) method turns out to be best for small numbers. The existing /spl ap/ O(n/sup 1.585/) method becomes better as the numbers get bigger. New methods that are /spl ap/ O(n/sup 1.465/) and /spl ap/ O(n/sup 2.404/) are presented. All of these methods can be generalized to multiplication and turn out to be faster than a fast Fourier transform (FFT) multiplication for numbers that can be quite large (>3,000,000 b). Squaring seems to be fundamentally faster than multiplication, but it is shown that T/sub mult/ /spl les/ 2T/sub sq/ + O(n).> Dan Zuras |
IEEE Symposium on Computer Arithmetic | 1 |
| 1988 | Integer Multiplication and Division on the HP Precision ArchitectureabstractIn recent years, many architectural design efforts have focused on maximizing performance for frequently executed, simple instructions. The authors describe how a small set of primitive instructions combined with what is considered careful frequency analysis and clever programming allows the Hewlett-Packard (HP) Precision Architecture integer multiplication and division implementation to provide adequate performance at little or no hardware cost.> Daniel J. Magenheimer, Liz Peters, Karl Pettis, Dan Zuras |
IEEE Trans. Computers | 4 |
| 1987 | Integer Multiplication and Division on the HP Precision ArchitectureabstractIn recent years, many architectural design efforts have focused on maximizing performance for frequently executed, simple instructions. Although these efforts have resulted in machines with better average price/performance ratios, certain complex instructions and, thus, certain classes of programs which heavily depend on these instructions may suffer by comparison. Integer multiplication and division are one such set of complex instructions. This paper describes how a small set of primitive instructions combined with careful frequency analysis and clever programming allows the Hewlett-Packard Precision Architecture integer multiplication and division implementation to provide adequate performance at little or no hardware cost. Daniel J. Magenheimer, Liz Peters, Karl Pettis, Dan Zuras |
ASPLOS | 4 |