Training and running inference of large neural networks comes with excessive cost and power consumption. Thus, realizing these networks as analog circuits is an energy-and areaefficient alternative. However, analog neural networks suffer from inherent deviations within their circuits, requiring extensive testing for their correct behavior under these deviations. Unfortunately, tests based on Monte Carlo simulations are extremely time- and resource-intensive. We present an alternative approach to proving the correctness of the neural network using formal neural network verification techniques and developing a modeling methodology for these analog neural circuits. Our experimental results compare two methods based on reachability analysis showing their effectiveness by reducing the test time from days to milliseconds. Thus, they offer a faster, more scalable solution for verifying the correctness of analog neural circuits.

We present the first work on the automated generation of reachset conformant models for analog circuits. Our approach applies reachset conformant synthesis to add nondeterminism to piecewise-linear circuit models so that they enclose all recorded behaviors of the real system. To achieve this, we present a novel technique to compute the required nondeterminism for the piecewise-linear models. The effectiveness of our approach is demonstrated on a real analog circuit. Since the resulting models enclose all measurements, they can be used for formal verification.

In contrast to the formal verification of digital circuits, analog formal verification requires appropriate tolerances of the device parameters. Enclosing these tolerances in set-valued models leads to unwanted overapproximation. In this paper, we present an automated modeling approach, which is applicable to nonlinear analog and mixed-signal circuits. We describe the behavioral circuit models as well as the device parameter variations and modeling errors by symbolic equations. We substitute these symbols with intervals and affine forms, respectively. In each case we provide semi-symbolic hybrid automata models. Then, we insert numerical values in these models for reachability analysis. The results of both reachability analyses are used to reduce the overapproximation.

In the era of advancing technology, increasing circuit complexity requires faster simulators for the verification step. The piece-wise linear simulation approach provides an efficient and accurate solution. In this paper, a state-of-the-art mixed-signal simulator is explained. The approach is extended to new exponential and quadratic stimuli. This requires a comprehensive derivation of mathematical equations, which remove the need for computationally expensive evaluation. The new stimuli are simulated in several circuits and compared to a conventional simulator. The result shows significant run-time acceleration with high accuracy. Therefore, it meets the industrial requirement, which demands simulation with various input forms and non-linear components.

Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today's analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This paper shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multirun simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phase-locked loop of an IEEE 802.15.4 transceiver system.

In a time when technology achievement in electronics proceeds fast and the subcircuits size on system on chips (SoC) are decreasing, a mixed-signal simulator is indispensable for the development of integrated circuits (IC). The PRAISE (Piecewise Rapid Analog Integrated Simulation Environment) approach is able to simulate mixed-signal circuits in SystemC Environment. Until now the PRAISE only supports simple mixed-signal configuration. In this paper we demonstrate different approaches for control system in mixed-signal circuits. We also expand PRAISE capabilities to simulate multiple analog and digital circuits. This allows modular systems and complex simulation behaviour. The accuracy and speed is compared to reference simulations utilizing traditional mixed-signal simulator.

The growing complexity of VLSI designs demands for continuous performance improvement of Electronic Design Automation (EDA) applications. Tradionally, part of this performance delta has been reached by leveraging the improvements in the single threaded performance of common processors. Unfortunately processor speeds have mostly plateaued in recent years. However, the advent of freely programmable GPUs allowed their use as highly parallel systems for a variety of computational use cases, making them an attractive device for reaching performance goals. In this paper, we introduce STP, a quadratic placement implementation, which leverages the computational power of GPUs as well as multicore CPUs in order to speed up execution.

On the contrary to the digital world, no coverage definition exists in the Analog/Mixed-Signal (AMS) context. As digital coverage helps digital designers and verification engineers to evaluate their verification progress, analog designers do not have such metrics. This paper proposes a set of different analog coverage metrics, which improve the confidence in AMS circuit verification. We will demonstrate, that no single overall coverage metric exists. However, as with digital coverage, the proposed analog coverage metrics could substantially help in rating the verification process. Illustrated by a complex AMS circuit example we will explore the limits of analog coverage methodologies as well as the benefits on different levels of abstraction ranging from transistor level up to system level.

We address the problem of formally verifying nonlinear analog circuits with an uncertain initial set by computing their reachable set. A reachable set contains the union of all possible system trajectories for a set of uncertain states and as such can be used to provably check whether undesired behavior is possible or not. Our method is based on local linearizations of the nonlinear circuit, which naturally results in a piecewise-linear system. To substantially limit the number of required locations, our approach computes linearized locations on-the-fly depending on which states are reachable. We can show that without the proposed on-the-fly technique, the conversion to piecewise-linear systems is infeasible even for a few nonlinear semiconductor devices (discrete state-space explosion problem). Our method is fully automatic and only requires a circuit netlist. Piecewise-linear systems have gained popularity not only for verification, but also for accelerated simulation of nonlinear circuits. Our method provides a guaranteed bound on the number of linearization locations that have to be explicitly computed for such a nonlinear circuit.

Reduction of interconnect length and thus reduction of power dissipation, and improvement of chip-performance is a key benefit of three-dimensional integrated circuits (3D ICs). However, to profit from 3D, carefully planning global interconnects (e.g. buses or wide IO) already at the floorplanning stage is very important. To this end, we present a new global interconnect driven 3D floorplanner which, different from previous work, simultaneously optimizes global interconnect routes, performs TSV placement, and accounts for fixed-outline floorplanning. For our 3D floorplanner, which is based on Simulated Annealing, we introduce an approach that efficiently guides the optimization process towards a valid and low-cost 3D floorplan solution. Experimental results on GSRC benchmarks demonstrate the efficiency of our tool.

Mission Profiles contain top-level stress information for the design of future systems. These profiles are refined and transformed to design constraints. We present methods to propagate the constraints between design domains like package and chip. We also introduce a cross-domain methodology for our corresponding constraint transformation system ConDUCT. The proposed methods are demonstrated on the basis of an automotive analog/mixed-signal application.

As fast non-simulation-based power estimation techniques, probabilistic simulation techniques were widely researched in the 1990s. Spatial and temporal correlations are commonly known as two fundamental challenges of these kinds of techniques. Previous work showed that spatial correlation could be coped with by means of bit-parallel simulation. For temporal correlation that has great impact on estimating glitches, previous work only showed that it could be considered by means of a glitch-filtering scheme which is an approximation algorithm, but did not answer the question whether temporal correlation could be overcome without any approximation. Our work extends conventional probabilistic simulation techniques and puts the essentials and extensions of probabilistic simulation into a theoretical framework. Based on the framework, this paper shows that modeling temporal correlation in probabilistic simulation without any approximation is only possible in theory. Therefore, an improved approximation of the exact method is proposed. Compared to the conventional probabilistic simulation, our prominently improved results prove the effectiveness of our approximation algorithm. At the end of this paper, the advantages and the bottlenecks of probabilistic simulation are concluded in general.

Analysis of mixed-signal circuits on system level demands for an accelerated simulation of analog blocks. We precompute state space representations that can be used to evaluate the circuit response and predict the occurrence of events triggered by analog components. Interfacing such models to SystemC digital simulation allows for very fast mixed-signal transient analysis. The key contribution of this paper is the dynamic generation of SystemC events from analog descriptions. We evaluate the performance of our approach using PWM (pulse width modulation) example circuits from the automotive domain which are interfaced to a SystemC microcontroller model. Accuracy and speed is compared to reference simulations utilizing traditional SPICE-like analog simulators. Our approach allows for a speedup of up to 70 for mixed-signal simulations compared to traditional analog and digital simulators.

The impact of parameter variations in integrated analog circuits is usually analyzed by Monte Carlo methods with a high number of simulation runs. Few approaches based on interval arithmetic were not successful due to tremendous overapproximations. In this paper, we describe an innovative approach computing transient and DC simulations of nonlinear analog circuits with symbolic range representations that keeps correlation information, and hence has a very limited overapproximation. The methods are based on affine and quadratic arithmetic. Ranges are represented by unique symbols so that linear correlation information is preserved. We demonstrate feasibility of the methods by simulation results using complex analog circuits.

This paper presents a novel arithmetic which allows calculations with fluctuating values. The arithmetic consists of a special representation of random variables and procedures for performing numerical operations between them. Given the distributions of initial random variables, the moments (such as expected value, variance and higher moments) of any calculated variable can be determined. Our approach is not limited to normal distributions and works with linear and nonlinear functions. Correlations between variables are taken into account automatically by the arithmetic. Examples show the accuracy and runtimes compared to Monte Carlo simulation.

As design complexity increases, todaypsilas HDL-based design flows push the capabilities of designers and tools to the limit. In recent years, ambitious efforts at increasing the abstraction level of formal design languages have been presented in order to overcome these limitations. Nevertheless, certain parts of all systems still have to be described in detail. Unfortunately, even small analog parts can slow down a global system simulation significantly. It is therefore necessary to generate abstract models with reduced but adequate result accuracy for these ldquobottleneckrdquo components. This paper presents a novel approach to the automated generation and evaluation of abstract behavioural models for automotive applications. Our methodology aims at achieving a convincing speedup in global system verification by accelerating the transient simulation of the crucial analog and mixed-signal components. The speedup results not only from an increased level of abstraction but also from a fast generation of circuit equations without the need for numerical integration. The approach is able to handle nonlinear circuits by employing piecewise linear models. The use of a SystemC interface will allow effortless integration into manifold simulation environments.

Non-tree routing experiences an increasing interest as technology scales into the nanometer range. Via and wire opens have become the main yield detractors considering random spot defects due to the additive manufacturing process of copper wires. Wiring networks containing loops offer some robustness against open defects which increases functional yield. State-of-the-art delay calculation enables the treatment of loops but does not provide an adequate solution for timing analysis in the presence of an open. If the delay in the presence of an open is not properly analyzed, a functional fail will be masked and replaced by a parametric fail which is only detectable applying delay testing. In this paper we present a new method to rapidly calculate the maximum delay if an open occurs in the net. For topologies consisting of non-adjacent loops we provide proof that the worst delay considering the Elmore delay metric can be found in 2N+1 delay calculations, whereas N is the number of loops in the net.

Since the IC technology scales down the effect of voltage drop/ground bounce becomes increasingly significant. Voltage drop and ground bounce can compromise the gate driving capability and degrade the IC performance, and even can cause IC functional failures. Hence, it is crucial to capture this effect efficiently and accurately in order to improve circuit reliability. in this paper, we propose efficient modeling techniques for analyzing power distribution in deep sub micron (DSM) ASIC designs. Current Source-based Model (CSM) and Voltage Controlled Resistor (VCR) are the key concepts in our approach. A basic prerequisite for the new approach are CMOS standard libraries that are pre-characterized with respect to the corresponding modeling requirements. This paper also presents an approach for this characterization step. The proposed techniques can efficiently handle multiple-input-switching (MIS), including single-input-switching events (SIS) and provide good analysis results compared to the reference with two orders of magnitude speedup, although the cell library pre-characterization is based on SPICE simulations. Our model is independent of the power network context, which implies that different power distribution networks may be analyzed based on the same model and the same cell characterizations. The run-time, memory and accuracy efficiency of the proposed method are demonstrated on an industrial design.

As technology rapidly scales, performance variations (delay, power etc.) arising from process variation are becoming a significant problem. The use of linear models has been proven to be very critical in many today's applications. Even for well-behaved performance functions, linearising approaches as well as quadratic model provide serious errors in calculating expected value, variance and higher central moments. This paper presents a novel approach to analyse the impacts of process variations with low efforts and minimum assumption. Circuit performance was formulated as a function of the random parameters and approximated it by Taylor expansion up to 4th order. Taking advantage of the knowledge about higher moments, the Taylor series was converted to characteristics of performance distribution. The experiments show that this approach provides extremely exact results even in strongly non-linear problems with large process variations. Its simplicity, efficiency and accuracy make this approach a promising alternative to the Monte Carlo method in most practical applications

In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges in multiple loops can be removed the augmentation efficiency is further improved. As a special feature, our algorithm keeps timing constraints which have not been considered by previous GMRTA algorithms.

This paper presents a new methodology for routing net bundles like busses and paired nets maintaining parasitic symmetry. It is mainly devoted to analog signal interconnect and can also be used for critical digital busses or clock signals. The PARasitic SYmmetric router (PARSY) is the first router that limits differential capacitances to a user defined value. Wirelength differences inside a net bundle are also equalized automatically. This routing methodology uses a novel module generator approach for wire implementation.

We propose a new placement model for global placement. This model uses probabilities to localize the cells. It enables arbitrary levels of placement abstraction. Wire-length estimations at any level can be derived from the model. We present a new placer, that uses a special variant of the proposed model. Examples show that the model properties improve placement quality.

A new and efficient combination of signal tracing and block recognition techniques for circuit analysis is proposed. It utilizes the benefits of both approaches to solve problems such as signal flow or gate recognition. The analysis process is easily controlled by a user definable rule set where ports, nets and block are attributed with types. After structural investigation a hierarchical netlist is produced providing block information as subcircuits. As an important feature, the algorithm allows the handling of optional ports as well. Thus, this flexible approach is applicable to various circuit types and works on several abstraction levels.