A fundamental responsibility of the leadership of a sovereign government is to create policies that enable the overall wellbeing of its citizens. This responsibility has many dimensions but certainly wealth generation through industrial competitiveness is a key component. Today a nation’s economic strength rests not only on ownership of saleable natural resources but increasingly on the technical capabilities and innovation capacities of its citizens. This is particularly true in an environment where technologies are constantly emerging to serve as the foundation for new industries. How does a relatively small nation-state, but with significant resources and aspirations, compete and excel in this environment? This article briefly describes an approach taken by the Abu Dhabi Emirate of the United Arab Emirates (UAE) to foster national competitiveness in selected emerging technologies in which the nation had previously had very little presence.

One of the remarkable technical achievements of the past 40 years has been the advances in complexity of the integrated circuit, driven primarily by an exponential rate of reduction in transistor feature sizes, thereby enabling the creation of electronic systems with steadily increasing functionality. The societal benefits in terms of economic growth from Moore's law scaling depend on a knowledge of learning curve cost reductions enabled by Moore's law. It might be possible to increase design efficiency to reduce nonrecurring engineering costs or to develop more cost-effective packaging technologies. The basic physics upon which a transistor operates might be altered 'to utilize other physical phenomena, such as electron spin, magnetic dipoles, photons, etc., to develop new classes of devices that would preserve Moore's law benefits.

In this paper, the historical effects and benefits of Moore's law for semiconductor technologies are reviewed, and it is offered that the rapid learning curve obtained to the benefit of society by feature size scaling might be continued in several different ways. The problem is that as features approach the range of a few nanometers, electron-based devices depart radically from the ideal switch and, in fact, become very leaky in the off state. It is argued that there are some short-term solutions involving more highly parallel manufacturing, increased design efficiency, and lower cost packaging technologies that could continue the steep learning curve for cost reductions that have historically been achieved via Moore's Law scaling. Another alternative might be to increase chip functionality by integrating devices that offer broadened chip functionality including, e.g., sensors, energy sources, oscillators, etc. A third alternative would be to invent an entirely new information processing state variable based on different physics, using electron spin, magnetic dipoles, photons, etc., to improve the performance and reduce switching energy for devices whose smallest features are on the order of a few nanometers. Each of these alternatives is being actively explored and an overview of each strategy and progress to date is given in the paper. A final alternative offered in the paper is to learn from information processing examples in nature, specifically in living systems. An E.coli cell of about one cubic micrometer volume is shown to be an incredibly powerful and energy-efficient information processor relative to the performance of an end-of-scaling silicon processor of the same volume. The paper concludes by pointing out some of the crucial differences between E.coli information processing and conventional approaches with the hope technologies can be invented using the hints offered by biosystems.

Many memory candidates based on beyond complementary metal-oxide-semiconductor (CMOS) nanoelectronics have been proposed, but no clear successor has yet been identified. In this paper, we offer a methodology for system-level analysis and address the relationship of the maximum performance of a given memory device type to device physics. The method is illustrated for the classical dynamic RAM (DRAM) device and for the emerging memory device known as the resistive RAM (ReRAM).

In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation." We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.