This paper focuses on high speed embedded SRAM design, especially on novel circuit technique to improve SRAM access time. A new two-stage sensing scheme which is able to reduce long interconnection metal line delay by transferring differential signals with half swing amplitude has been proposed. Post-layout simulation results show that the long distance signal transmission time has been decreased by 45%. Chip measurement shows the access time has been decreased by 23% at the expense of little area penalty (1.3%) and some read power penalty (about 16%) mainly caused by 2nd-stage sense amplifiers.

A wireless force measurement system is presented in this paper. The system, which is used during the operation of Total Knee Arthroplasty(TKA), is designed to assist surgeons to determine the proper position of the knee implants and consequently enhance the success ratio of the treatment. It consists of three parts: a device to measure and transmit force data, a receiver and a terminal to display the force data in real time. The transmitter communicates with the receiver by 2.4GHz Radio Frequency (RF) signal. The system consumes no more than 17mA current with 3V voltage supply typically. So it can work with a button battery cell. Experimental results show that the performance of the system meets the requirements.

A low-power CMOS capacitance-to-digital converter for capacitive sensors array is presented. It consists of a 16-channel MUX, a front-end with wide dynamic range for capacitance-voltage conversion and a novel voltage-pulses convertor. This novel circuit charges the measured capacitor indirectly and converts it into a proportional voltage, and then produces a 16-bits pulses-formed single-line output with multi-steps quantization method. The circuit can operate under 1.2V to 3.6V voltage supply for single battery application. The maximum input is 350pF with 0.75ms/ch update rate and 90μA power consumption when the operating clock is 100KHz. The chip has been design and fabricated in 0.18-μm 1P6M CMOS process with active area of 640×630μm2.

Integrated circuit (IC) design for a wireless BCI system is put forward in this paper. The system is composed of an electrode, a stimulator, antennas, and an integrated circuit including a preamplifier, an analog to digital converter (ADC), a current mode digital to analog converter (DAC), a transceiver and a micro control unit (MCU). The system is closed loop, which can detect and record electroencephalogram (EEG) signals, send the signals to computer wirelessly, and generate stimulating signals according to analysis results from the computer. A 16-bit ADC is designed and some non-idealities parameters (e.g. kT/C noise, 1/f Noise and so on) are given. Sub-threshold circuit technology is used to realize ultra low-power MCU. Both of the ADC and the MUC are verified by simulation results. Next work will include the design of the preamplifier, IDAC, and a single chip design integrating all the circuits.