Security of a computer system has been traditionally related to the security of the software or the information being processed. The underlying hardware used for information processing has been considered trusted. The emergence of hardware Trojan attacks violates this root of trust. These attacks, in the form of malicious modifications of electronic hardware at different stages of its life cycle, pose major security concerns in the electronics industry. An adversary can mount such an attack with an objective to cause operational failure or to leak secret information from inside a chip-e.g., the key in a cryptographic chip, during field operation. Global economic trend that encourages increased reliance on untrusted entities in the hardware design and fabrication process is rapidly enhancing the vulnerability to such attacks. In this paper, we analyze the threat of hardware Trojan attacks; present attack models, types, and scenarios; discuss different forms of protection approaches, both proactive and reactive; and describe emerging attack modes, defenses, and future research pathways.

While scan-based testing achieves a high fault coverage, it requires long test application times and substantial tester memory, in addition to the overhead in chip area and high test power. Functional testing, on the other hand, suffers from low coverage but can be applied at-speed. In this paper, we propose a novel three-step design-for-test (DFT) methodology which enhances the performance of functional testing to a great extent. In the first step we expand the state space of the circuit beyond functionally reachable space without scan or reset. These new states create conditions to activate/propagate fault effects that are otherwise hard-to-detect. Since structural correlation between D flip-flops (DFFs) of a circuit restricts its state space variation, the second step consists of partitioning the DFFs into different groups that helps to break such correlations. In the third step, we make internal hard-to-observe points in the circuit more observable by directly XORing them with selected primary outputs. This method can be applied at-speed (since no scan shifting is involved) saving significant amount of test application time, with comparable area overhead as scan-based DFT. Our experiments on large ISCAS'89 and ITC'99 benchmarks show that we are able to achieve very high non-scan fault coverages while simultaneously reducing the test application time (114×) as compared to scan based techniques.

Scan-based DFT is the de-facto industrial practice for testing integrated circuits (ICs). Variations in the scan architecture to improve test metrics have been the primary focus in recent years. In this paper, we propose a new nonscan DFT in which a subset of the circuit flip-flops are made directly loadable from the primary inputs and another subset of flip-flops are made observable at the output via a state compactor. In this architecture, multiple flip-flops may share the same primary input in the loading mode. A load-enable pin is added to distinguish the direct-loading mode from the functional mode. With a modest area overhead, this architecture offers several attractive features, including (1) at-speed testing, which eliminates the need for scan-shifting and would thus capture delay-related defects, (2) low test data volume and test application time, as we no longer need to store all the scan and response data, (3) high coverages, since the low-testability flipflops are made to be loadable and/or observable, and (4) low test power. Experimental results on large ISCAS'89 circuits validate the aforementioned metrics with 10× to 100× reduction in test application time with respect to Illinois Scan.

High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of data compression thereby reducing both test data volume and test application time. However, the fault coverage achieved in the Broadcast Mode of the ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in the ILS are either ad-hoc or rely on test pattern information from an apriori ATPG run. In this paper, we present a novel low cost technique to construct ILS scan configuration for a given design. It efficiently utilizes the circuit topology and tries to optimize the flip-flop assignment to a scan chain location without compromising the fault coverage in the Broadcast Mode. Thus, it eliminates the need of an apriori ATPG run or any test set information. Experimental results on the ISCAS'89 benchmark circuits show that the proposed ILS configuration method can achieve on an average 5% more fault coverage in the Broadcast Mode and an average 15% more reduction in total test data volume and test application time than the existing methods.

Testing the genuineness of a manufactured chip is an important step in an IC product life cycle. This becomes more prominent with the outsourcing of the manufacturing process, since the manufacturer may tamper the internal circuit behavior using Trojan circuits in the original design. Traditional testing methods cannot detect these stealthy Trojans because the triggering scenario, which activates it, is unknown. Recently, approaches based on side-channel analysis have shown promising results in detecting Trojans. In this paper, we propose a novel test generation technique that aims at magnifying the disparity between side-channel signal waveforms of tampered and genuine circuits to indicate the possibility of internal tampering. Experimental results indicate that our approach could magnify the likelihood of Trojans 4 to 20 times more than existing side-channel analysis based approaches.