We propose a real-world-oriented interface called the "mirror metaphor interaction system". The display shows a mirror image from a camera facing a user, and the user can "touch" objects without making direct contact with the display. The "touched" object displays a menu or works directly. Objects can be placed in a remote room as well as in the user's room, and can also be moved around in a room. The user can therefore control equipment or interact with objects anywhere through the display of the system by combining images from local and remote places translucently. Our demonstration shows how the interface makes it easy to establish contact with movable objects in a remote room by "touching" them in the display.

A human activity that expresses one's emotion is significantly important in non-verbal communications. Human body motion such as a dance performance is one of the important factors in expressing such an emotion. An effective method to extract emotional information in real time from dance images is described. A novel heuristic function is also proposed to evaluate the degree of harmony between two dancers. As a typical application, a dance system called MIDAS that interactively combines dancers' images with video, sound, and CG characters is introduced. MIDAS can visualize how well dancers are in harmony with each other and encourage their expressions.

3D object data transfer was optimized to accelerate interactive 3D scene design and virtual-space layout applications. In these applications, downloading many 3D objects reduces the interactivity of the clients. We used level-of-detail based loading sequences and timing control methods to interleave data downloading and interactions. Experiments showed that the maximum interval between interactions was up to 6.42 times shorter.

A timing-driven global routing algorithm applicable to high-speed bipolar LSI's is proposed. Path-based timing constraints are directly modeled and routing paths are selected using novel heuristic criteria to minimize area as well as to satisfy the timing constraints by keeping track of the critical path delay and channel densities. Using bipolarspecific features, this router can be applied to Gbit/s LSI's. Experimental results shows that the average delay improvement was 17.6% and the algorithm is quite promising.

Global and detailed routing algorithms that minimize crosstalk noise between signal lines are described. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in the independent area of the digital nets as much as possible. Both the global and detailed routers minimize the number of signal-line crossovers, especially for analog nets, as these crossovers are dominant in crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. The experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.>

In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan." In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented. The initial block placement is obtained by an attractive and repulsive force method (AR method), and the subsequent block packing process is performed by gradually moving and reshaping blocks with chip boundary shrinking. The chip area estimation is performed by using individual block area calculations from empirically obtained equations. A set of interactive commands is also provided to facilitate the manual optimization processes using a color graphic terminal. By processing several practical VLSI circuits, it is shown that the method is very effective for handling various kinds of blocks and is able to reduce the design effort required to achieve the chip floor plan.

A global router for gate array LSI's is described, which is intended to perform an interaction between placement and routing such that the features of one may be incorporated into those of another. This router is to generate for each net an interconnection pattern of channel segments in such a unified way of taking all interrelated interconnection requirements into account at once. A main objective of the router is not only to minimize the maximum of the local routing densities but also to distribute all the wiring requirements over channels evenly, in order to attain 100-percent interconnections within a limited area. An implementation result of the router is also shown.