With the rapidly increasing demands for high-speed and high-density electronic products, complexity and size of the associated circuits have increased significantly in the recent years. The large size of these circuits poses major challenges for simulation in terms of excessive CPU cost. To address this, a parallel circuit simulation algorithm has been recently developed that allows modern multicore processors to be exploited to realize higher parallel scalability with an increasing number of CPUs. In this paper, several methods have been proposed to improve efficiency and flexibility during the partitioning of analog circuits. The proposed methods reduce the constraints for partitioning, allowing a more efficient set of partitions to be found, which improves scalability when used in a parallel implementation.

This paper presents a fast algorithm for transient simulation of power grids in very large scale integration systems using waveform relaxation (WR) techniques. Novel partitioning methods and convergence accelerators are developed for fast convergence of WR iterations when applied to power grid networks. Unlike the direct solvers, the new method is highly parallelizable and scales well with the increasing number of CPUs, leading to significant speed-ups. Numerical examples are presented to demonstrate the validity and efficiency of the proposed method.

The large number of ports in an interconnect struc- ture is a critical limiting factor when applying model-order reduction. This is due to the fact that the size of the reduced model grows rapidly with increasing the number of ports, lead- ing to large and dense circuit matrices. To address this problem, a novel method based on transverse partitioning and waveform relaxation is proposed for passive model-order reduction of massively coupled large multiport interconnects. The new method effectively replaces the tightly coupled multiport reduced model with decoupled 2-port subcircuits. In addition to preserving the advantages of model-order reduction, the compu- tational complexity of the new method grows only linearly with the number of lines.

This paper describes a new algorithm for the analysis of high-speed interconnects characterized by frequency-dependent per-unit-length parameter matrices. The proposed technique is based on using the idea of integrated congruence transform to construct a reduced-order system for the interconnect. The reduced-order system offers simple time-domain ordinary differential equations that can be embedded into conventional circuit simulators. The proposed algorithm provides a new approach to perform implicit moment matching on a system described by a mixed set of linear differential algebraic equations. This feature offers a high accuracy in the reduced system over a wide frequency range. The passivity of the reduced-order system is guaranteed. Numerical results demonstrate the validity of the proposed technique.

Time-domain macromodeling of high speed interconnects characterized by distributed transmission lines has generated immense interest during the recent years. It has been demonstrated that, preserving passivity of the macromodel is essential to guarantee a stable global transient simulation. In this paper, a SPICE compatible closed-form passive macromodel for distributed transmission lines is presented. The proposed method enables representation of the distributed stamp in terms of simple delay and resistive elements. The new method while guaranteeing the passivity of the macromodel, provides significant speedup, and enables easy implementation. Necessary formulation and validation examples are given.