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A. R. Teene

dblp:20/251 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.011982
WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1982
Electronic design automation › CAD framework
design tool integration
0.011982
WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1982
Electronic design automation › hardware verification and test › logic simulation
gate-level simulation
0.011982
WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1982

Methods — techniques the papers use, named apart from their topics

process simulation · 0.0device simulation · 0.0circuit simulation · 0.0
YearPublicationVenuePosition
1982 WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits
abstract
Recent advances in integrated circuit technology have involved process development, device, and circuit optimization under scaled design rules. It is advantageous to be able to simulate the overall circuit performance under different conditions. A simulator which performs this task at the logic gate level becomes important. This paper describes such a simulator for digital bipolar integrated circuit families: WATPAC. WATPAC uses the process simulator SUPREM, the device simulator BIPOLE, and the circuit simulator WATAND. The input parameters to WATPAC are entered interactively. These consist of fabrication process parameters, layout design rules, a specification of the logic family, and a WATPAC predefined logic function. The WATPAC output consists of overall circuit performance data for the simulated function block. The output of WATPAC also includes the intermediate outputs of the process simulator, device simulator, and the circuit simulator.
A. R. Teene, Mohamed I. Elmasry, David J. Roulston
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1