Adam Levinthal

dblp:20/2535 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 55% Processor architecture and microarchitecture · 46%
Computer graphics and multimedia
1 paper
Rendering · 50% Image and video processing · 50%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
graphics accelerator
0.021987
Parallel Computers for Graphics Applications · ASPLOS 1987
Chap - a SIMD graphics processor · SIGGRAPH 1984
Processor architecture and microarchitecture
SIMD
0.011987
Parallel Computers for Graphics Applications · ASPLOS 1987
Rendering
graphics hardware
0.011984
Chap - a SIMD graphics processor · SIGGRAPH 1984

Methods — techniques the papers use, named apart from their topics

crossbar network · 0.0SIMD · 0.0
YearPublicationVenuePosition
1987 Parallel Computers for Graphics Applications
abstract
Specialized computer architectures can provide better price/performance for executing image processing and graphics applications than general purpose designs. Two processors are presented that use parallel SIMD data paths to support common graphics data structures as primitive operands in arithmetic expressions. A variant of the C language has been implemented to allow high level language coding of user applications on these processors. High level programming support is designed into the processor architecture that implements parallel object data typing and parallel conditional evaluation in hardware.
Adam Levinthal, Pat Hanrahan, Mike Paquette, Jim Lawson
ASPLOS1
1984 Chap - a SIMD graphics processor
abstract
Special purpose processing systems designed for specific applications can provide extremely high performance at moderate cost. One such processor is presented for executing graphics and image processing algorithms as the basis of a digital film printer. Pixels in the system contain four parallel components: RGB for full color and an alpha channel for retaining transparency information. The data path of the processor contains four arithmetic elements connected through a crossbar network to a tessellated scratchpad memory. The single instruction, multiple data stream (SIMD) processor executes instructions on four pixel components in parallel. The instruction control unit (ICU) maintains an activity stack for tracking block-structured code, using data-dependent activity flags for conditional disabling subsets of the ALUs. Nested loops and if-then-else constructs can be programmed directly, with the ICU disabling and reenabling ALUs on the basis of their individual status bits.
Adam Levinthal, Thomas K. Porter
SIGGRAPH1