Field programmable dual-Vdd interconnects are effective in reducing FPGA power. We formulate the dual-Vdd-aware slack budgeting problem as a linear program (LP) and a min-cost network flow problem, respectively. Both algorithms reduce interconnect power by 50% on average compared to single-Vdd interconnects, but the network-flow-based algorithm runs 11x faster on MCNC benchmarks. Furthermore, we develop simultaneous retiming and slack budgeting (SRSB) with flip-flop layout constraints in dual-Vdd FPGAs based on mixed integer linear programming, and speed-up the algorithm by LP relaxation and local legalization. Compared to retiming followed by slack budgeting, SRSB reduces interconnect power by up to 28.8%.

Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns

Field programmable dual-Vdd interconnects are effective to reduce FPGA power.Assuming uniform length interconnects,existing work has developed time slack budgeting to minimize power based on estimating the lower bound of power reduction using dual-Vdd for given time slack.In this paper,we show that such lower bound estimation cannot be extended to mixed length interconnects that are used in modern FPGAs.We develop a technique to estimate power reduction using dual-Vdd for mixed length interconnects, and apply linear programming (LP)to solve slack budgeting to minimize power for mixed length interconnects.Experiments show 53%power reduction on average compared to single-Vdd interconnects.Furthermore,this paper presents a simultaneous retiming and slack budgeting algorithm to reduce power in dual-Vdd FPGAs considering placement and.ip-.op binding constraints.The algorithm is based on mixed integer and linear programming (MILP)and achieves up to 20%power reduction compared to retiming followed by slack budgeting.We propose a runtime e fficient flow to apply simultaneous retiming and slack budgeting only when it is necessary.To the best of our knowledge,this paper is the first in-depth study of simultaneous retiming and slack budgeting for dual-Vdd programmable FPGA power reduction while considering layout constraints.

Programmable logic devices such as FPGAs are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than ASICs and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications such as those in consumer and automotive markets. Our design uses the Xilinx Spartan-3 low-cost FPGA as a baseline and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode, and wakes up from standby mode in approximately 100ns.

Increasing power densities in Field Programmable Gate Arrays (FPGAs) have made them susceptible to thermal problems. The advent of platform FPGAs has further exacerbated the problems by increasing the power density variations on the FPGA fabric. Therefore, we need to characterize the die temperature of platform FPGAs. In this paper, we first estimate the temperature distribution within a Virtex-4 FPGA by feeding the block power numbers in an architecture-level temperature simulator calibrated to reflect a real FPGA package. We analyze the impact of different hard-wired blocks on the temperature profile, and observe that they introduce intra-die variation in temperature of up to 20°C. Next, we evaluate the influence of placement on temperature. Our experiments indicate a decrease in peak temperature by changing the placement of hard blocks, especially the high-speed transceivers. We further propose an iterative placement technique to reduce the peak temperature, and apply it on real designs. Finally, we propose alternate organizations of the hard blocks in the FPGA fabric to reduce temperature.

Power consumption in FPGA designs calls for power-aware design and power budgeting early in the design cycle. In this work, we leverage the FPGA architecture to present an efficient and accurate methodology for pre-silicon dynamic power estimation of FPGA-based designs. Our methodology uses device-level simulations to characterize a coarse-grained architectural model and incorporates architectural parameters to estimate the dominant wire capacitance. Such an approach not only reduces the need for tedious and time consuming silicon characterizations but ensures accurate pre-silicon power predictions. We apply the methodology to estimate the power consumption of a state-of-the-art Spartan-3™ FPGA family, evaluate the estimation results against silicon measurements, and present a detailed power breakdown of the FPGA. Our results find that the routing resources and the clock to consume the maximum power.

As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unused multiplexers used in the interconnect fabric. This work focuses on reducing the leakage of these unused multiplexers by controlling their inputs. We investigate the design issues involved in implementing such a technique and also show experimental results demonstrating the effectiveness of our approach.

In this session, we will first present an overview of new challenges in commercial FPGA architecture design with an emphasis on the circuit and architecture issues for power at current and upcoming process nodes. Today’s 90nm FPGAs utilize techniques such as programmable shut-down of unused resources at the architectural level and multiple threshold voltages and gate-oxides at the circuit level. At 65nm and 45nm new techniques will need to target not only power mitigation but process variation in power and timing and their impact on yield and manufacturability.

We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-tables) that allows a logic signal in an FPGA design to be interchanged with its complemented form without any area or delay penalty. We apply this property to select polarities for logic signals so that FPGA hardware structures spend the majority of time in low leakage states. In an experimental study, we optimize active leakage power in circuits mapped into a state-of-the-art 90nm commercial FPGA. Results show that the proposed approach reduces active leakage by 25%, on average.

FPGAs are being increasingly used in a wide variety of applications. While power optimization has been only of secondary importance in many FPGA applications, growing importance of leakage in FPGAs designed in 90nm and below makes it imperative to treat power optimization as a first class citizen. In this paper, we propose a leakage-saving technique for FPGAs that involves dividing the FPGA fabric into small regions and switching on/off the power supply to each region using a sleep transistor in order to conserve leakage energy. Specifically, the regions not used by the placed design are supply gated. Next, we present a new placement strategy to increase the number of regions that can be supply gated. Finally, the supply gating technique is extended to exploit idleness in different parts of the same design during different time periods. Our experiments with different region sizes using various commercial and academic designs indicate that the proposed optimization outperforms conventional placement, and reduces leakage power consumption significantly.

One of the most compelling challenges of the next decade is the "last-meter" problem, extending the expanding data network into end-user data-collection and monitoring devices. PicoRadio supports the assembly of an ad hoc wireless network of self-contained mesoscale, low-cost, low-energy sensor and monitor nodes. While technology advances have made it conceivable to deploy wireless networks of heterogeneous nodes, the design of a low-power, low-cost, adaptive node in a reduced time to market is still a challenge. We present a design methodology for PicoRadio Networks, from system conception and optimization to silicon platform implementation. For each phase of the design, we demonstrate the applicability of our methodology through promising experimental results.

Low-energy protocol processing is a crucial issue in next generation wireless systems. In modern wireless system design, this problem is tightly coupled with the signal processing needs. Fierce market competition and inventive wireless applications are imposing stricter design requirements in energy consumption, cost, size, and flexibility. To deal with these unique constraints, we incorporate the platform-based design methodology to deal with these constraints by advocating reusability. This paper presents this methodology, and its application on PicoRadio, a cutting-edge wireless system. In particular, we describe the design of a reconfigurable architecture optimized for protocol processing.

Atmospheric scientists need to observe fluctuations in the ionosphere, both to probe the underlying atmospheric physics and to remove the effects of these fluctuations from other measurements. We have built an FPGA-based, pipelined array processor that allows us to make these observations in real-time, using passive radar techniques. Our array processor time-multiplexes 16 multiply-accumulators across 1536 radar ranges, performing a pipelined correlation and integration of the radar signal for each range. A DSP-based postprocessor generates real-time range-Doppler profiles of the ionospheric targets.

Communication designs form the fastest growing segment of the semiconductor market. Both network processors and wireless chipsets have been attracting a great deal of research attention, financial resources and design efforts. However, further progress is limited by lack of adequate system methodologies and tools. Our goal in this paper is to provide impetus for development of communication design techniques and tools. The first part addresses network processors (NP) that we study from three viewpoints: application, architecture, and system software and compilation tools. In addition to summary of main issues and representative case studies, we identify main system design issues. The second part of the tutorial focuses on wireless design. The main emphasis is on platform-based design methodology that leverages on functional profiling, architecture exploration, and orthogonalization of concerns to facilitate low-power wireless communication systems. The highlight of the paper, an in-depth study of the state-of-the-art wireless design, PicoRadio, is used as explanatory design example.