Spreadsheet languages, which include commercial spreadsheets and various research systems, have had a substantial impact on end-user computing. Research shows, however, that spreadsheets often contain faults. Thus, in previous work we presented a methodology that helps spreadsheet users test their spreadsheet formulas. Our empirical studies have shown that end users can use this methodology to test spreadsheets more adequately and efficiently; however, the process of generating test cases can still present a significant impediment. To address this problem, we have been investigating how to incorporate automated test case generation into our testing methodology in ways that support incremental testing and provide immediate visual feedback. We have used two techniques for generating test cases, one involving random selection and one involving a goal-oriented approach. We describe these techniques and their integration into our testing environment, and report results of an experiment examining their effectiveness and efficiency.

DIGITAL's Alpha 21264 processor is a highly out-of-order, superpipelined, superscalar implementation of the Alpha architecture, capable of a peak execution rate of six instructions per cycle and a sustainable rate of four per cycle. The 21264 also features a 500 MHz clock speed and a high-bandwidth system interface that channels up to 5.3 Gbytes/second of cache data and 2.6 Gbytes/second of main-memory data into the processor. Simulation-based functional verification was performed on the logic design using implementation-directed, pseudo-random exercisers, supplemented with implementationspecific, hand-generated tests. Extensive functional coverage analysis was performed to grade and direct the verification effort. The success of the verification effort was underscored by first prototype chips which were used to boot multiple operating systems across several different prototype systems. Keywords Alpha, microprocessor, verification, validation, architecture, pseudo-random, coverage an...

The advanced architecture of the Alpha 21264 microprocessor compelled the verification team to invent far-reaching techniques to achieve the goal of booting multiple operating systems on first silicon. These techniques, built on traditional verification methodology, exposed a number of esoteric bugs prior to tape-out. Verification engineers took focused testing, pseudo-random testing, and coverage analysis to new levels in order to meet the challenge of verifying a highly out-of order, superscalar machine. A new hybrid exerciser and a method for predicting the future enhanced pseudo-random testing. A new way of looking at coverage analysis was devised. Random behavior was added to hand-coded rests, several methods were created for tackling atomic operations, and a shadow reference model was written for the most advanced branch predictor implemented to date in a commercial microprocessor. Verification techniques were also expanded to include test pattern generation and post-silicon debugging.