By introducing amplify‐and‐forward relaying into a cognitive radio system, typical cognitive relay networks are studied for the optimisation problems of the spectrum and power allocation. By applying the mixed spectrum access of overlay and underlay approaches, an interference evaluation strategy is proposed to use different spectrum and power allocation methods while the secondary users (SUs) are located in different service regions of the primary users (PUs). In the interference evaluation strategy, the service area of the PUs is divided according to the possible interference strength of the PUs from the SUs compared with the location‐aware strategy in which the service area is divided only by the location information. An optimal power allocation algorithm is developed to maximise the throughput of the SUs under the condition of anti‐interference performance of the PUs and the total power constraints of the SUs. A type of computing algorithm that joins the subgradient and the Newton's method is used in order to resolve the complex optimisation problem. Numerical results show that the performance using the interference evaluation strategy, such as the throughput, the power consumption, and the energy efficiency, outperforms that using the location‐aware strategy.

On-chip routers are power hungry components. Besides exploiting current CMOS-based power-saving techniques, it is also desirable to investigate the power saving potential enabled by new technologies and devices. This paper investigates the potential of exploiting the emerging spin-electronics based MTJ (Magnetic Tunnel Junction) devices with application to on-chip router modules, in particular, buffers and crossbars. To this end, we build MTJ models, design circuits based on mixed MTJ-CMOS devices, and evaluate their switching power consumption, using their pure CMOS counterparts as the baseline. Our study shows that the new technology can significantly improve power efficiency for buffers but the gain for crossbars is less clear.

With the real-valued sequences, a new kind of Code Hopping Code Division Multiple Access (CH-CDMA) communication systems is proposed for anti-interception. While the sequence parameters are the same, the number of the real-valued sequence sets are much more than those of the traditional integer sequence, therefore, the codes for hopping are no longer in serious deficiency as they used to be, which makes the performance of anti-interception improved greatly. Moreover, using real-valued sequences with Quasi-Zero Correlation Zone (QZCZ) may eliminate the Inter-Symbol Interference (ISI) and Multi-Access Interference (MAI) so as to overcome the far-near effect and improve the performance of anti-interference.

A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.