There is a growing demand for low-cost and effective test solutions to support state-of-the-art analog and mixed-signal systems that are continuously increasing in complexity and functionality, while decreasing in product cost. This innovative practice session highlights various aspects of design for test (DfT) in high-complexity, analog-dominated systems with three talks that focus on: DfT in power management integrated circuits (ICs), an alternative testing method to analog test bus, and pre-silicon built-in self-test (BIST) verification, where BIST is used to monitor complex mixed-signal systems. These talks will be given by industry experts from Dialog Semiconductor, Xilinx, and Texas Instruments.

Clock power accounts for between 15% and 30% of a chip's power budget today. Due to this reason, demands for reducing power consumption makes dual-edge clocking attractive. However, clock domain crossings (CDCs) in dual-edge logic poses some unique problems for commonly used DFx features. Solutions such as lock-up latches are not directly applicable. First, scan-chain CDCs are considered for which two solutions are presented. Second, two problems related to clock-stoppage for scan-dump are considered and solutions to these problems are proposed and analyzed.

This paper presents a Concurrent Sampling (CS) method for measuring a multitude of analog DC voltages concurrently using local digitization. Boolean results after digitization are routed in an IJTAG compatible fashion. Analog quantities are no longer routed across the die, thus overcoming several limitations of Analog Test Buses. Furthermore, the proposed method enables real-time measurement of analog voltages, thus addressing a growing need for Automotive test and reliability. The proposed method is applied to an analog circuit consisting of widely used analog blocks such as a bandgap reference and an operational amplifier. Transistor level simulation results demonstrate that the proposed method is functional and the drawbacks of the ATB are no longer present.

Latest SOC trends include multiple asynchronous clock domains, each covering large silicon areas. Clock-Stop & State-Dump (CSSD) is a commonly used silicon debug technique that relies on stopping clocks and reconfiguring flip-flops as one or more scan chains. This paper describes an architecture for stopping clocks deterministically to allow safe state preservation before reconfiguring a circuit. Conditions for determinism are defined and a design IP to implement CSSD is described. Considerations for supporting an IP-SOC design methodology are also specified. The design was implemented and validated in Xilinx' 16nm FPGA family.

A new use for ring-oscillators (ROs) is proposed by which PMOS and NMOS transistor strengths can be measured and monitored in the field. A new metric, based on RO duty-cycle is defined. This new metric, along with RO-frequency, offers a way to profile and bin transistors based on their drive strengths. With ROs configured from payload transistors, along with the natural programmability of FPGAs, this strength based profiling can be done in the field at a level of granularity that is not possible with existing methodologies. New applications of the metrics and the profiling methodology include use of on-die ROs as a (a) monitor and control for duty-cycle sensitive designs, (b) replacement for scribe-line test structures, and (c) sensor for payload transistor characteristics over life-time.

This paper presents a clock-less digital pulse stretcher which takes a short pulse as input and produces a detectable pulse that is longer than a required minimum duration. The proposed structure has high sensitivity to input pulse width and height and is capable of detecting deep sub-nanosecond pulses. This enables a wide variety of applications ranging from characterization of radiation-induced single-event transients to detection of glitch attacks and tamper resistance for security. Implementation of the proposed pulse stretcher in a 130nm process validates the analytical relationships between the input and output pulse. Simulation results show that the design can capture an input pulse with width larger than 50ps and height greater than 300mV. The shortest pulse that can be detected by the design can readily scale down with technology due to the digital nature of the circuitry.

Welcome to 2017, the thirty-fifth in a series of annual symposia that focuses on innovation in the field of testing of integrated circuits and systems.

FPGAs have evolved rapidly over the past decade with a significant increase in size and complexity. Today's FPGA is indeed a system-on-chip (SOC) with a wide variety of hardened functionality, multiple asynchronous clock domains and widening interactions among different parts of the chip. It is commonplace to find applications that transfer data and control across clock-domains. This growing complexity, coupled with shrinking design cycles, has turned debug and verification into a critical design concern. Although software analysis tools have made significant progress over the years, this is not the case for debugging applications running on FPGAs. This paper describes a framework that enables non-intrusive application hardware debugging in the presence of multiple asynchronous clock domains. It offers full observability at minimal area and performance cost. The proposed approach uses Readback to retrieve the entire state of the circuit, a feature available in one form or another, in most commercial FPGAs today. Features such as single stepping and waveform reconstruction offer the same level of debug capability for applications accelerated on FPGAs, as simulation tools do for RTL implementations.

Although there are standards for DFT, there are none for Design for Debug and Validation (DFD/DFV) of silicon in systems. Many semiconductor companies have standardized DFD/DFV architectures and features within their own products, however these are proprietary solutions. The panel will explore whether or not these solutions share common requirements and will debate whether the industry would benefit from any standardization, and what to standardize. Examples are standard debug infrastructure IP, bridges to software debug and support for EDA automation.

A new industry-wide trend is the presence of multiple on-die power-supplies that are not directly connected to external supplies. Examples are internally-regulated supplies and power-gated supplies. This trend has brought to fore, the problem of testing for shorts between such internal supply grids and other (internal or external) supply grids. Today, presence of such shorts often results in excessive current draw from the tester and eventually results in burnt probe-tips adding to the overall cost of test. This paper proposes a classification of shorts defects involving internally regulated supplies. Two classes of solutions for mitigating or eliminating the problem are described. Methods for maximizing sensitivity of the solutions under leakage and probe-tip constraints are also described.

Test vehicles are commonly used to understand the characteristics of a new process node. The ability to precisely identify and isolate defects is a key requirement during yield learning on these vehicles. Efficiently utilizing the fanouts in a design is critical to get a smaller pfa area. In this talk, we introduce the concept High Observability Patterns. High observability patterns target the detection of a defect in multiple patterns using multiple and different observe points. This allows the diagnostics engine to more precisely identify where the defect is and thus reducing the PFA area.

Achieving automotive quality requires IC tests that achieve 100% coverage of potential defects. With new cell-aware digital test pattern generation techniques and the simple stuck-at fault model, this has proven practical for digital circuitry, but there is no equivalent for mixed-signal circuitry. A simple but realistic analog defect model is described, based on industrial observations and theory. It is consistent with previous proposals, but has novel differences that make it suitable for schematic and layout-extracted netlists and more efficient to simulate. A couple of examples show its effectiveness.

Ever larger on-die memory arrays for future processors in CMOS logic technology drive the need for dense and scalable embedded memory alternatives beyond SRAM and eDRAM. Recent advances in nonvolatile spin transfer torque (STT) RAM technology, which stores data by the spin orientation of a soft ferromagnetic material and shows current induced switching, have created interest for its use as embedded memory. STTRAM exhibits scalable write current, sufficient read margin and nonvolatility or persistence, all of which make it an attractive solution for last level cache, embedded cache or even main memory. In an era of on-die non-volatile storage, new defect, disturb and fault mechanisms need to be comprehended during characterization as well as manufacturing tests. The first part of the talk will introduce STTRAM and review the fundamentals of the cell design, the read and write mechanisms as well as recent advances in technology, which make it a potential successor to eDRAM, followed by how variations and thermal noise limit the material and cell design space. The second part will discuss new test models that would be required for such non-volatile storage, the necessity of large scale data collection and analysis, as well as the need for BIST and on-line testing, and conclude with challenges and opportunities in STTRAM testing that lie ahead of us.

While IC speed binning is commonplace today, power binning is a relatively new practice and doing that on an automatic test equipment (ATE), without the aid of functional patterns, is even more rare. As with speed binning, power binning depends on measuring power of multiple components in each IC and using the measurements in a model to predict actual power dissipation of the chip. Power dissipated by embedded SRAMs, especially under activity levels found in normal operation, is critical to power binning. This paper describes a method for measuring the normal functional power of embedded SRAMs by re-using memory BIST and JTAG circuitry in an ATE environment, contributing to power binning at wafer probe.

The impact of di/dt noise and static IR drop on at-speed scan testing has been reported in literature. Delays of paths can be impacted during delay testing by IR drop and di/dt noise in ways that change the delay ordering of paths. This, in turn, affects the ability of such tests to catch certain delay defects and impairs its use for speed binning. It is important, therefore, to address IR drop during delay tests. This paper proposes an instrumentation methodology for a design based on launch-off-capture delay tests to control the time interval between shift and capture cycles. This mechanism improves speed characterization of devices and achieves a higher capture frequency compared with traditional methods. It also addresses reduction of di/dt noise during capture. The proposed scheme is realized by (i) pipelined scan-enable and (ii) a deterministic launch-and-capture method for the tile under test. This mechanism has been implemented on silicon and experimentally observed to increase the speed of a device between 8% and 24% relative to traditional methods.

Power dissipation of an LSI circuit during scan testing, especially at-speed scan testing, can be several times higher than that during functional operations. Excessive test power causes hot spots and/or severe IR drop that may lead to chip damage, undue yield loss, or reliability degradation, especially for low-power LSI circuits. As a result, it is becoming increasingly important to reduce test power by lowering test-induced toggle activity in order to make scan test “power-safe”. However, with the stress on reducing toggle activity during scan test one might question: Have we gone too far? Should we reduce toggle activity below functional levels? Should we even plan for many test sets with different toggle activities? Can the test power problem be solved by existing DFT and ATPG solutions? What's missing in today's solutions? What's next for low-power testing? This panel provides an interactive forum to discuss these critical questions with industry experts from both semiconductor and EDA companies. It helps practitioners and researchers alike in their quest for more effective and more efficient solutions to the test power problem.

In this paper we motivate the explicit validation of hold-time violations in silicon and propose a method for doing so. New hold-time failure model and test pattern generation methodologies are defined.We outline conditions under which these tests can be applied reliably. We present results of applying these test patterns on a microprocessor and discuss the implications of intermittent failures on the relevance of hazards during timing analysis.

An emerging trend in microprocessor architecture for servers is to design chips with multiple processor cores on a chip called chip multi-processors (CMPs). Due to the short design cycle time and large size of these chips, the design-for-testability and testing of such chips is a major challenge. In this paper we describe a hierarchical DFT architecture for UltraSPARC/spl trade/ CMPs that is scalable with number of processor cores and can be implemented in a very short design cycle time. The DFT architecture allows testing of the processor cores individually for diagnosis as well as concurrently to reduce test application time and thus test cost. The DFT architecture can be easily ported across CMPs with different numbers of processor cores as well as to higher order CMPs designed by putting together CMPs.

Memory model generation for test has traditionally been a complex, manual process subject to the test engineer's skill and the designer's cleverness. The paper describes an automated memory model generation and validation framework for embedded memories of custom digital designs. The proposed framework allows the description of the characteristics of the memory through a GUI or a language called Memory Description Language (MDL). The framework accepts user-specified information to generate a customized memory primitive with simulation, phase-accurate, and test views. The generated memory primitive undergoes a two-step validation process to ensure its correct functionality and is then used as a library primitive to describe embedded memories.

The problem of generating DC parametric test patterns while reducing ground bounce is considered. A clear tradeoff is identified between test time and the amount of ground bounce. An algorithm generating input DC tests with minimum ground bounce is proposed. Furthermore, we propose algorithms for reducing ground bounce for output DC tests under test time constraints based on the amount of information available. Experimental results prove that these algorithms not only reduce ground bounce but also keep test time within reasonable limits.

We propose a very simple and fast CAD tool to check whether a binary counter can reproduce a predetermined set of test patterns in a reasonable time. Given a test matrix T, the tool uses column merging, complementation, and permutation so that the distance between the starting and the finishing vector of the corresponding counter is minimized. The hardware overhead of the proposed approach is by far lower than that of any other existing approach. Although it is computationally difficult (NP-hard) to obtain the absolute minimum distance, we present an algorithm which in the absence of don't cares in the test matrix, finds an appropriate column merging, complementation, and permutation that guarantees the distance is never more than twice as large as the best possible. In the presence of don't cares, the latter algorithm forms the basis of a powerful heuristic. Experiments on various test sets on benchmark circuits show that the exact number of clock cycles needed for a binary counter to reproduce all the patterns for the hard-to-detect faults compares favorably with the expected number yielded by existing Weighted Random LFSR-based approaches which have significantly higher hardware overhead.

Article A branching process model for observability analysis of combinational circuits Share on Authors: Sarma Sastry Electrical Engineering Systems Department, University of Southern California, Los Angeles, CA Electrical Engineering Systems Department, University of Southern California, Los Angeles, CAView Profile , Amitava Majumdar Electrical Engineering Systems Department, University of Southern California, Los Angeles, CA Electrical Engineering Systems Department, University of Southern California, Los Angeles, CAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 452–457https://doi.org/10.1145/127601.127711Online:01 June 1991Publication History 4citation121DownloadsMetricsTotal Citations4Total Downloads121Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Motivated by the work of K. Kim et al. (1988) and A. Krasniewski and S. Pilarski (1989), the problem of test efficiency in random testing of sequential circuits using built-in self-test (BIST) techniques is addressed. It is shown that, given a circuit with n primary inputs and the goal of maximizing expected pattern coverage, different pattern-sampling distributions for its 2/sup n/ possible patterns can be partially ordered. The exact distributions for pattern coverage for both equiprobable and nonequiprobable pattern-sampling distributions are derived. Approximations for pattern-coverage distributions under equiprobable pattern-sampling conditions and corresponding numerical results are presented. A limiting distribution function for pattern-coverage distribution is derived. The authors also present numerical results on confidence levels for obtaining a specified pattern coverage. The distribution for the number of test cycles (R) required to achieve a specified pattern coverage is also derived. The authors derive and use the expression for the expected value of R to illustrate the increase in the effect of achieving a specified coverage j as j increases.>

A linear systolic array with fault-tolerant capabilities is described. Fault tolerance is achieved by using triple time redundancy. The array is capable of undergoing reconfiguration and can operate in a gracefully degradable mode. The concept of algorithm remapping on degraded (smaller) arrays is integrated with that of graceful degradation to obtain a general fault-tolerance technique. A new technique for restructuring algorithms and executing them on a degraded array is discussed. The requisite modifications of the interconnection, switching, and control structures to achieve fault tolerance are discussed. Reliability analysis of the system is carried out, and the reliability is compared to that of nonredundant systolic arrays. Finally, the average performance of the system, with running time and throughput as performance metrics, is estimated.>

Two pseudo-concurrent fault diagnostic approaches, namely, a roving spare technique and an inverse residue checking technique, and a testing strategy for processing elements in a high-speed signal processing system, are studied. The system consists of an array of identical (differing only in programmable coefficients) chips that perform complex arithmetic operations. Expressions for fault coverage and average fault latency using random tests for the two diagnostic techniques are obtained. A tradeoff between hardware overhead and average fault latency is identified. A comparison of the two techniques with respect to a set of attributes is presented. The fault-diagnostic techniques described were found to be suitable for implementation on a generalized-sidelobe-cancellor architecture mainly because of the memoryless property of the computations.>