An FMCW frequency synthesizer features fractional bandwidth boosting (FBWB), phase-noise correlation and cancellation, a digitally-controlled oscillator (DCO) with fast look-up table (LUT) initialization scheme, ultra-fast low-power MMD. With a bandwidth-boosting factor of 2.4, the prototype measures a continuous chirp fractional bandwidth (FBW) of 67.2%, frequency tuning range (FTR) of 111%, PN of −121.5dBc/Hz at 1MHz offset from 7.25GHz, jitter of 88 fs, and 0.06ms LUT convergence time while consuming 31.7 mW, corresponding to FOMTof −204.7dB.

Rotary traveling-wave oscillators (RTWOs) inherently feature multiphase outputs and low phase noise. Conventionally RTWOs are studied with a distributed model, which deviates from practical implementations whenever the quasi-rotary traveling wave nature emerges due to the prominent structural discontinuity. In this paper, an LC-based segmented elementary circuit (SEC) model is employed for the oscillator analysis. Interestingly, the transmission line (TLine) presents an extrinsic quality factor (Q), rather than its well-known intrinsic Q, to the resonator. Hence, an extrinsic-Q-enhanced (EQE) TLine featuring a hollow ground plane underneath is proposed. For validation, a 16-phase quasi-rotary traveling-wave oscillator (QRTWO) with the EQE TLine is designed and implemented in a 65nm CMOS process. The prototype measures a frequency tuning range from 28.3 to 32.9 GHz while only consuming 5 mW from a 0.9-V supply. At 32.9 GHz, it achieves phase noise of –124.2 dBc/Hz at 10-MHz offset. The corresponding figure-of-merit (FoM), FoM with tuning range (FoM$_{\mathrm {T}})$, and FoM with number of phases (FoM$_{\mathrm {P}})$are 187.5, 191.1 and 199.6 dB, respectively, all are the highest comparing with existing multiphase VCOs at similar frequencies. The QRTWO occupies a core area of 0.12 mm2 excluding pads.

This paper presents a millimeter-wave (mmW) frequency doubler based on complementary push-push (CPP) configuration achieving wideband, low-power and high-efficiency operation. Conventional push-push (PP) frequency doublers typically rely on half-wave rectification and suffer from performance compromise between the desired output and the DC current consumed. To mitigate this issue, a simple but effective CPP frequency doubling scheme is proposed to realize full-wave rectification, attaining enhanced output harmonic current and improved fundamental rejection without extra power consumption. At the output, an implicit dual-resonance (IDR) network featuring inherent resonant frequency alignment is employed to efficiently combine the harmonic power generated by the CPP transistors. Implemented in a 65-nm CMOS process and occupying a core area of 0.04 mm2, the proposed frequency doubler prototype measures conversion loss of < 10 dB from 53 to 78.5 GHz at 0-dBm input, while consuming 21.5 mW from a 1-V supply.

A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based g m -boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm 2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.

A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.