Accurate modeling and estimation of the threshold voltages of the flash memory can facilitate the efficient design of channel codes and detectors. However, most flash memory channel models are based on Gaussian distributions, which fail to capture certain key properties of the threshold voltages, such as their heavy-tails. To enhance the model accuracy, we first propose a piecewise student's t-distribution mixture model (PSTMM), which features degrees of freedom to control the left and right tails of the voltage distributions. We further propose an PSTMM based expectation maximization (PSTMM-EM) algorithm to estimate model parameters for flash memories by alternately computing the expected values of the missing data and maximizing the likelihood function with respect to the model parameters. Simulation results demonstrate that our proposed algorithm exhibits superior stability and can effectively extend the flash memory lifespan by 1700 program/erase (PE) cycles compared with the existing parameter estimation algorithms.

Abstract The error‐correcting performance of multi‐level‐cell (MLC) NAND flash memory is closely related to the block length of error‐correcting codes (ECCs) and log‐likelihood‐ratios of the read‐voltage thresholds. Driven by this issue, this paper optimizes the read‐voltage thresholds for MLC flash memory to improve the decoding performance of ECCs with finite block length. First, through the analysis of channel coding rate and decoding error probability under finite block length, the optimization problem of read‐voltage thresholds to minimize the maximum decoding error probability is formulated. Second, a cross‐iterative search algorithm to optimize read‐voltage thresholds under the perfect knowledge of flash memory channel is developed. However, it is challenging to analytically characterize the voltage distribution under the effect of data retention noise. To address this problem, a deep neural network (DNN)‐aided optimization strategy to optimize the read‐voltage thresholds is developed, where a multi‐layer perception network is employed to learn the relationship between voltage distribution and read‐voltage thresholds. Simulation results show that, compared with the existing schemes, the proposed DNN‐aided read‐voltage threshold optimization strategy with a well‐designed Low Density Parity Check (LDPC) code can not only improve the program‐and‐erase endurance but also reduce the read latency.

The differential chaos shift keying with code index modulation (CIM-DCSK) using Walsh codes can increase the data rate, but error rate performance degrades over practical multipath channel with high delay spread. To tackle this drawback, this paper proposes a parallel CIM-DCSK (PT-CIM-DCSK), where the first time slot is used to transmit the chaotic reference sequence, and the second slot is used to transmit the multiple sequences carrying data bits. In particular, multiple$q$chaotic sequences are added for data transmission in parallel, and each sequence is modulated by CIM-DCSK with$m_{c}$bits. By exploiting the quasi-orthogonal characteristics of permuted chaotic signals, the interference between$q$sequences can be remarkably suppressed. In this way, given the data rate, PT-CIM-DCSK can achieve a larger length of Walsh segment than the CIM-DCSK, since its parallel transmission compensates the rate. In addition, the error performance of the proposed scheme over the multipath Rayleigh fading channel is theoretically analyzed. The theoretical and consistent simulation results demonstrate that the PT-CIM-DCSK can obtain significant performance gains over the conventional CIM-DCSK, and the gain can be up to 5 dB in multipath fading channel with high delay. This is because the larger Walsh segment of PT-CIM-DCSK provides the enhanced robustness against multipath effect. The performance superiority of the proposed scheme is further verified in practical ultra-wideband (UWB) wireless industrial scenarios, which suggests promising for low-cost and low-complexity wireless communication applications.

Abstract This paper investigates error correction in two‐dimensional (2‐D) intersymbol interference (ISI) channels using polar codes. 2‐D channels offer high data storage capacity compared to traditional one‐dimensional (1‐D) channels but suffer from greater ISI effects. Error correction codes can be used to mitigate the effects of ISI in 2‐D data storage systems and improve their performance and reliability. Polar codes achieve the symmetric capacity for the class of binary‐input discrete memoryless channels (B‐DMCs). A post‐processing technique is proposed to improve the performance of polar codes in the 2‐D ISI channel. The simplified successive cancellation (SSC) polar decoder is useful for data storage systems owing to its good waterfall region performance, low error floors and good throughput rates and is therefore adopted for the study. Simulation results indicate that the proposed technique has an error correction performance comparable to some existing decoders and has better performance than other decoding techniques.

In this paper, we propose an effective read-voltage optimization method for multi-level-cell (MLC) NAND flash memory to improve the performance of error correcting codes (ECCs) with finite blocklength. Specifically, we first obtain the maximal channel coding rate achievable at a given blocklength and error probability of quantized channel. Based on this finite-blocklength channel-coding rate (FCR), we convert the optimization problem into minimizing the error probability instead of the channel coding rate. Then, we develop a cross iterative search (CIS) method and the genetic algorithm to solve this optimization problem. In our simulations, for a well-designed LDPC code, our read-voltage optimization method improves program-and-erase (PE) endurance up to about 900 and 600 cycles against the maximizing the mutual information (MMI) and entropy-based optimization methods, respectively, at a frame-error-rate (FER) of 2×10-4.

For two-way relay channel-coded physical network coding (CPNC) systems with sufficiently low code rate, the separate complete decoding (SCD) scheme outperforms the joint channel-physical network coding (JCNC) scheme. Hence, this paper addresses the design of protograph LDPC codes to approach the SCD-based CPNC capacity. In fact, due to virtual erasures induced by CPNC transmission, the conventional protograph that approaches point to point (P2P) AWGN capacity may not perform well in SCD-based CPNC channel in terms of error rates. We then use the finite-length EXIT chart to calculate iterative decoding threshold of a joint code graph formed by two codes in the SCD. Furthermore, we investigate the serial separate complete decoding (S-SCD) and parallel separate decoding (P-SCD). Simulation results show that with the S-SCD, the proposed protograph codes have within 0.9 dB of their capacity limits for rates from 1/3 to 3/5.

The authors study the performance of protograph low‐density parity‐check (LDPC) codes over two‐dimensional (2D) intersymbol interference (ISI) channels in this study. To begin with, the authors propose a modified version of finite‐length (FL) extrinsic information transfer (EXIT) algorithm so as to facilitate the convergence analysis of protograph codes. Exploiting the FL‐EXIT analyses, the authors observe that the protograph codes optimised for 1D ISI channels, e.g. the 1D‐ISI protograph code, cannot maintain their advantages in the 2D‐ISI scenarios. To address this problem, the authors develop a simple design scheme for constructing a family of rate‐compatible improved protograph (RCIP) codes particularly for 2D‐ISI channels, which not only outperform the 1D‐ISI protograph code, but also are superior to the regular column‐weight‐3 code and optimised irregular LDPC codes in terms of the convergence speed and error performance. More importantly, such RCIP codes benefit from relatively lower error‐floor as well as linear encoding and fast decoding. Thanks to these advantages, the proposed RCIP codes stand out as better alternatives in comparison with other error‐correction codes for ultra‐high‐density data storage systems.

Non‐binary low‐density parity‐check (NB‐LDPC) codes can be directly constructed by using algebraic methods, or indirectly constructed by mapping well‐designed binary parity‐check matrices to non‐binary parity‐check matrices. Given the Tanner graph (TG) of a NB‐LDPC code, the selection of edge weights in the TG significantly affects the performance of the NB‐LDPC code. The authors introduce an edge weight distribution (EWD) parameter for the TG of NB‐LDPC codes. By utilising particle swarm optimisation (PSO), the EWD is optimised and it has been demonstrated that the optimal EWD approaches a two‐element distribution for large field size and high average variable‐node degree. With the optimised EWD, the authors construct a class of field‐compatible LDPC (FC‐LDPC) codes over GF( q ) whose parity‐check matrices only include elements 0, 1 and 2, and can be encoded and decoded over different field sizes. The simulations demonstrate that the performance of the proposed FC‐LDPC codes improves monotonically with increasing field size, and significantly outperforms that of the corresponding algebraic NB‐LDPC codes or NB‐LDPC codes generated with uniform distribution of non‐zero elements over GF( q ).

An algorithm based on the fitting of modified Extrinsic Information Transfer (EXIT) chart is proposed to calculate the thresholds of low-density parity-check (LDPC) codes optimized for the two-dimensional (2D) intersymbol interference (ISI) channels encountered in high-density magnetic recording, such as bit-patterned magnetic recording (BPMR) and two-dimensional magnetic recording (TDMR). The modified EXIT chart algorithm determines the LDPC threshold by fitting the EXIT curve of the variable node decoder (VND) combined with 2D detector (2D-DET) to the EXIT curve of the check node decoder (CND). Both the optimal Bahl-Cocke-Jelinek-Raviv (BCJR) 2D-DET and reduced-complexity Gaussian-approximated iterative row-column 2D-DET are considered.

In this paper, we study the problem of devising distributed bilayer quasi-cyclic Low-Density Parity-Check (QC-LDPC) codes for cooperative relaying communications. One theorem in designing the bilayer QC-LDPC code without small stopping sets and small girth is proposed, which significantly simplifies the bilayer QC-LDPC codes design. Based on the proposed theorem and the two-hop decode-and-forward (DF) relaying protocol, in which the relay node is used to assist the source to transmit extra parity bits to the destination, a new design method for a distributed irregular bilayer QC-LDPC is developed. It is demonstrated that the overall performance can be improved by using the proposed approach in DF-based cooperative relaying communications. Finally, it is shown that the proposed construction method also leads bilayer QC-LDPC codes to have a bigger minimum distance.