Bio-inspired Spiking Neural Networks (SNNs) offer potential for scaling to pattern recognition tasks while accommodating low-cost applications. By adapting SNNs to reinforcement learning (RL) schemes, new development avenues open for energy-aware structures. This work employs a real-time RL system with a SNN core for MNIST classification. The proposed architecture enhances a previously developed simple binary decision-making 5-bit integer hardware architecture to handle more complex image recognition tasks at the edge, while maintaining its energy efficiency and high learning accuracy. Although the clock frequency (45 MHz) and dynamic power dissipation (270 mW) scale as expected with network growth on an Intel MAX 10 10M50DAF256C8GES FPGA, the number of cycles for a learning or classifying operation does not change significantly, demonstrating the multi-cycle architecture’s favorable scaling characteristics for low-energy classification problems.

Neuromorphic circuits and systems involving spiking neural networks (SNN) have resulted in disruptive advances in performance/joule for relevant applications. A novel reinforcement learning (RL) digital hardware architecture is presented in this work that achieves energy consumption improvements through three fundamental techniques: The first two techniques comprise reduction in the complexity of the arithmetic unit for the optimization of recurring synapse and neuron cores in the network array, which is inspired by "crude" nature of the building blocks in the biological neurons that are tolerant to inaccuracy and noise. As the third technique, the RL SNN middle (hippocampus) layer is equipped with a simple scratchpad to facilitate temporal hysteresis in synaptic plasticity during the RL processes of long-term potentiation/depression (LTP / LTD). This feature is inspired by the non-temperamental behavior of biological synapses. The intelligent allocation significantly reduces learning time in a given task. Implementation on Intel Cyclone IV FPGA demonstrated significant advantages in cost, power dissipation and execution time, resulting in more than two orders of magnitude benefit in energy consumption for a context-dependent learning task on a 16-node 3-layer RL network presented in the literature.

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design.

This paper presents a low-power and area-efficient finite field multiplier based on irreducible all-one polynomials (AOP). The proposed architecture implements the AOP multiplication algorithm in three stages, which are reduction network, AND network (multiplication), and three input XOR tree (accumulation), while state-of-the-art implementations distribute reduction, multiplication and accumulation operations in a systolic array. The optimization reduces the overall number of sequential instances and provides lower pipeline latency compared to literature. This leads to the reduction of power dissipation and area for a targeted system clock frequency. Both the previously reported and the proposed architectures have been implemented in Verilog for three different and relevant binary field sizes using TSMC 130-nm standard cell library from Artisan Components, and have been synthesized with a 100 MHz system clock frequency target using the Cadence Genus Synthesis tool. The proposed architecture offers 23%, 41%, and 20% reduction in average leakage, dynamic power, and area, respectively, compared to state of the art. The pipelined latency advantage can be translated to further power dissipation reduction by targeting a lower clock frequency in applications where single AOP multiplication execution time is more important than pipeline throughput. Thus, the proposed architecture is better suited for energy-efficient portable systems, including wireless sensors.

The fully implantable cochlear implant (FICI) interface circuit proposed in this work senses sound harmonics from 8 different piezoelectric cantilever sensors, and generates pulse width modulated biphasic current outputs to stimulate the auditory neurons. Signals from the piezoelectric sensors are amplified, rectified, and sampled. The sampled voltage is held and converted to current by a novel logarithmic voltage-to-current converter. The current is then digitized with a current comparator to determine the width of the generated biphasic current pulses. Continuous interleaved sampling (CIS) is used as the stimulation technique for 8 channels operation. The system is designed and implemented in 0.18 μm HV CMOS process. Measurements show that the circuit is able to generate 15 to 62.5 μs biphasic current pulses with 400 μA peak amplitude, as the input range varies from 60 dB to 105 dB sound pressure level. The total power consumption of 82 and 513 μW have been measured at 70 dB input for 1-channel and have been extrapolated for 8-channels configurations, respectively, which are the lowest powers for FICI interface electronics to the best of our knowledge.

This paper presents an ultralow power interface circuit for a fully implantable cochlear implant (FICI) system that stimulates the auditory nerves inside cochlea. The input sound is detected with a multifrequency piezoelectric (PZT) sensor array, is signal-processed through a front-end circuit module, and is delivered to the nerves through current stimulation in proportion to the sound level. The front-end unit reduces the power dissipation by combining amplification and compression of the sensor output through an ultralow power logarithmic amplifier. The amplified signal is envelope detected, and fed to a voltage-controlled current source as a reference for stimulation current generation. The single channel performance has been tested with a thin film pulsed-laser deposition (PLD) PZT sensor for sound levels between 60- and 100-dB sound pressure level (SPL). The proposed front-end signal conditioning unit, which can support different back-end stimulators, dissipates only 25.4 and 51.2 μW based on measurement, for 1- and 8-channel operation, respectively. This represents the lowest in the literature. The interface generates linear stimulation current of 110-430 μA for the given sound range. The single-channel and eight-channel stimulator consume 105 and 691 μW, respectively, for 110-μA biphasic stimulation current.

This work presents the implementation of the self-leakage test, a new approach for unconnected I/O leakage testing. It provides a path for leakage current through the on-chip leakers and uses the voltage drop at the pad to detect a pass/fail condition. A detailed methodology for defining the self-leakage test specifications has been developed. Preliminary silicon data shows that self-leakage test methodology provide a viable method for high-volume monitoring of I/O leakage at minimal on-die DFT (design-for-test) overhead.

This work presents the next generation AC IO loopback design for two Intel processor architectures. Both designs detect I/O defects with 20 ps resolution and 50 ps jitter for up to 800 MHz bus speed. Even though the implementations differ in some aspects to accommodate two different bus architectures, the same prudent considerations for high speed operation, minimum test inaccuracy, and low implementation costs apply to both.