This work presents a time register designed for time-domain signal processing, employing a delay line in a ring configuration topology combined with a digital counter to achieve a high dynamic range. The proposed architecture supports both addition and subtraction operations, offering a practical framework for understanding the implementation of such functionalities in the time domain. The register is capable of efficiently processing signals with durations ranging from picoseconds to milliseconds and demonstrating feasibility for physical implementation.

This paper introduces a novel time register for time-domain signal processing, utilizing a delay line within a ring configuration topology and a digital counter to achieve high dynamic range. The proposed design was implemented and simulated using the AMS 350 nm CMOS process and tested under nominal supply voltage of 3.3 V. Corner simulation, considering supply voltage, temperature, and process variations, demonstrated an error rate below 2% for inputs exceeding 50 ns. A key advantage of the proposed solution is that its range can be easily scaled by increasing the number of counter bits, while the layout area overhead introduced by the counter remains minimal. This is the first CMOS time register capable of efficiently processing signals from picoseconds to milliseconds, providing an output pulse equal to the input pulse, and being feasible for physical implementation.

This article presents a novel time-domain implementation of the second-order Goertzel frequency analyzer, which can be extended for use in infinite impulse response (IIR)/finite impulse response (FIR) filters. A set of time-domain arithmetic circuits, including a one-step time register (TR), time amplifier (TA), time adder, and unit delay operator (${z}^{-1}$), are introduced to overcome the limitations of conventional time-domain filters. The working principles and nonidealities of each block are analyzed and compared with the existing methods. The proposed filter is implemented in a 180-nm CMOS process with a 0.9-V supply voltage. The designed frequency analyzer is tunable to extract the amplitude and phase angle of signals up to 400 Hz. Simulation results, targeting a 280-Hz signal at a 19.88-kHz sampling frequency, demonstrate that the filter can detect the amplitude and phase of a voltage signal in the time domain with an error below 5%. The filter achieves a resolution of$76.7~\text {dBV/s}$, consumes less than$24~\mu \text {W}$of power, and the estimated silicon area is almost$0.828~\mathrm {mm}^{2}$.

In this article, a novel approach for performing multiply–accumulate (MAC) operations in the time-domain is presented. The Internet of Things, machine learning, and 5G are driving up demand for this type of operation, which is also crucial for many applications that rely on digital signal processing (DSP). For accomplishing this operation, a fully time-domain MAC unit capable of consecutively multiplying two input time pulses and adding them to previously stored signals is proposed. The main component of the circuit is the time register, which adds and stores time information. The MAC unit design is realized in commercial 180-nm CMOS process and occupies an estimated area of about$3167 \mu \text{m} ^{\mathrm{ 2}}$. The proposed circuit can perform MAC operations with less than 5% error for a dynamic range (DR) of 19 ns, presenting an$R ^{\mathrm{ 2}}$linearity of over 0.99. Its power consumption is 1.72 mW from a 1.8-V supply.

This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip multiprocessor proposals were designed and compared for Xilinx FPGAs using MicroBlaze processors: one based on NoC and the other based on shared memory/bus. One of the main findings is the communication performance evaluation of NoC for parallel computing applications. The comparison results show that an efficient implementation of NoC on FPGA can improve communication speed by up to seven times with low area overhead, according to the data size and the number of processors connected to the network.