DOA estimation using an array of sensors requires precise knowledge of the wavelength /spl lambda/ of the incident signal. This paper considers the case when /spl lambda/ is unknown or imprecisely known and shows that an inherent ambiguity prevents a linear array from resolving wavelength and DOA simultaneously. This problem does not arise in non-linear arrays, and an algorithm is presented for estimating DOA and wavelength.>

We demonstrate the feasibility of a distributed implementation of the Goldberg-Tarjan algorithm for finding the maximum flow in a network. Unlike other parallel implementations of this algorithm, where the network graph is partitioned among many processors, we partition the algorithm among processors arranged in a pipeline. The network graph data are distributed among the processors according to local requirements. The partitioned algorithm is implemented on six processors within a 15-processor pipelined message-passing multicomputer operating at 5 MHz. We used randomly generated networks with integer capacities as examples. Performance estimates based upon a six-processor pipelined implementation indicated a speedup between 3.8 and 5.9 over a single processor.>

This paper presents a theoretical framework for scheduling of subcircuit simulation in a multirate simulation environment. We show that event-driven simulation, selective-trace, and latency are subsumed by this framework.

XPSim (formerly known as SuperCrystal), a multirate, event-driven circuit simulator suitable for large MOS VLSI circuits, is described. XPSim incorporates both static and dynamic partitioning of the circuit. Each partitioned subcircuit is numerically solved with a new integration method-the exponential function method. The voltage waveforms produced by this method are piecewise exponentials. Currently, XPSim supports up to a third-order explicit method. Preliminary tests indicate that XPSim exhibits a significant speedup over SPICE while retaining similar accuracy and is able to handle large circuits.>

We propose a language that can be used to describe configuration of rectilinear Steiner trees. Given a set of points in a plane indexed by integer coordinates, the execution of a pattern-description in our language will list a number of Steiner trees spanning the points. The Steiner trees that are produced will be used as input to a linear-program type global router for VLSI gate-arrays [10]. Other applications for our language include routing printed circuit boards and generating Steiner tree configurations for simulated-annealing type global routers [11].