Ascon was selected as the standard of lightweight cryptographic algorithm by NIST in 2023, and it is expected that Ascon will be used in IoT devices in the future. Still, the vulnerability of the Ascon circuit against side-channel attacks (SCAs) remains an issue. A threshold implementation has been proposed, but the hardware cost is non-trivial. In this paper, we propose a masking-based protection mechanism. Experimental results show that the proposed method can effectively prevent correlation power analysis (CPA) with low hardware overhead.

Physical Unclonable Functions (PUF) have been proposed as security primitives for security applications. However, previous studies indicate that strong PUFs are vulnerable under machine learning (ML) based modeling attacks as such algorithms can achieve extremely high prediction accuracy. The reliability of PUFs is also a concern. In this paper, we propose to enhance the reliability and resistance to modeling attacks from the system perspective. With the help from the server, we can improve the PUF reliability by using error correction code. Furthermore, we propose to use S-boxes to confuse the attackers. A novel attack strategy based on stronger neural networks is proposed to assess the security. Experimental results show that the proposed method can improve PUF reliability and unpredictability with low hardware overhead.

In this study, we develop an innovative federated framework for erasable itemset mining to address the challenges of horizontal federated learning in data mining and resolve the shortcomings of the previous algorithm. The framework is based on a client-server architecture, in which clients from multiple data sources collaborate to effectively integrate information. The proposed algorithm is divided into two parts, including the client-side mining and the server-side aggregation. During the client-side mining stage, the algorithm introduces quasi-erasable itemsets to collect additional useful information, facilitating the integration of results on the server side. In the server-side aggregation stage, the algorithm employs a boundary strategy, effectively utilizing the clients' quasi-erasable and erasable itemsets to improve the accuracy of the results. Experimental results demonstrate that the proposed method not only effectively mines complete knowledge but also ensures data-privacy protection.

Digital microfluidic biochips (DMFBs) can effectively reduce the cost of biochemical analysis and improve experimental efficiency, as they are easy to carry, use fewer reagent samples and have high precision. Paper-Based Digital Microfluidic Biochips (PB-DMFBs) are a branch of microfluidic biochips. This technology prints ink containing carbon nanotubes on special paper to form electrodes and control wire, so the manufacturing cost and time required are far less than the traditional digital microfluidic chip, in which droplets move between two control layers. However, the chip-level synthesis of PB-DMFBs becomes more challenging because all circuits of PBDMFBs are printed on a single paper layer. Furthermore, current PB-DMFB designs must address various issues, including fabrication cost, reliability, and safety. Therefore, a more flexible method for the chip-level synthesis of PB-DMFBs is needed. In this paper, we propose a chip-level synthesis method of PB-DMFBs based on reinforcement learning. Double Deep Q-learning Networks (Double DQN) are suitable for agents to select actions and estimate actions, and then obtain optimized comprehensive results. Experimental results demonstrate that the proposed method is not only effective and efficient for chip-level synthesis, but also scalable to applications with high reliability and safety requirements.

Paper-based digital microfluidic biochip (PB-DMFB) technology provides a promising solution to many biochemical applications. However, the PB-DMFB manufacturing process may suffer from potential security threats. For example, a Trojan insertion attack may affect the functionality of PB-DMFBs. To ensure the correct functionality of PB-DMFBs, we propose a watermarking scheme to hide information in the PB-DMFB layout, which allows users to check design integrity and authenticate the source of the PB-DMFB design. As a result, the proposed method serves as a countermeasure against Trojan insertion attacks in addition to proof of authorship.

In the wafer testing process, the needle tips for circuit probing (CP) should always be contamination-free. However, continuous testing will affect measurement quality since probe tips are exposed to contaminating substances. Thus, proper prober needle cleaning mechanism plays an important role. Three circuit probing cleaning challenges may result in yield loss. First, prober needle cleaning are currently defined by prior experience and the occurrence of die failure. Second, the process is inefficient since there is no prediction mechanism for embedded and bonded debrisprior to a test. Third, over cleaning reduces the needle's life. To address these issues, we propose a framework based on real-time die contact resistance analysis. The framework employs supervised machine learning to develop a recognition mechanism for detecting sudden foreign material buildups and monitoring needle degradation based on the sensor data so as to enhance yield of wafer probing and increase the expected probe life cycle.

Paper-based digital microfluidic biochips (PB-DMFBs) have emerged as the most promising solution to biochemical applications in resource-limited regions. However, like silicon chips, the reliability of PB-DMFBs is affected by physical defects. Even worse, since electrodes, conductive wires, and droplet routings are entangled on the same layer, multiple faults may occur simultaneously. Such faults not only cause waste of samples and human resource but also affect the correctness of the diagnostics. In this paper, we propose a reliability scheme with emphasis on design-for-reliability (DfR) and probability-based fault tolerance to ensure the correct functionality of PB-DMFBs with multiple faults.

Physical Unclonable Functions (PUF) provide a lightweight secure primitive. However, it is well known that PUFs are vulnerable to machine learning based modeling attacks (MA). A lot of efforts have been devoted to develop MA-resistant PUFs, while MA techniques are also evolving. In this paper, we propose to protect PUF-based authentication systems by providing an intrusion detection mechanism. By replacing some responses with the check information only known to the server and the PUF, any attacks will trigger alerts to the server. The proposed method provides an active protection mechanism so that the verifier can initiate an intrusion detection process to determine whether the prover is an attacker in disguise. In this way, the proposed method can provide an early alert so as to achieve another layer of protection. Experimental results show that the proposed mechanism can effectively provide alerts after PUFs being attacks.

Fully programmable valve arrays (FPVAs) have emerged as a new technology commonly used for biochemical applications. FPVAs have the programmability to perform any bioassay as long as users obtain the fluidic-level synthesis results to configure the fluid loading. Users can purchase a bioassay and the corresponding synthesis result from any bioassay provider. However, the distributed design stages are vulnerable to security threats. Trojans are the most critical threats since they can be inserted in any design stage. Even worse, Trojans would not result in a significant deviation from the original synthesis results, while they can affect the bioassay execution dramatically. In this paper, we propose the six Trojan models for FPVAs and a systematic method for Trojan insertion. In the experiments, we insert Trojans into ten test cases. Most of the Trojan-inserted synthesis results are similar to Trojan-free ones in terms of the efficiency metrics. In other words, the experimental results show that the proposed Trojans for FPVAs are stealthy.

Local defect patterns (LDP) in wafer maps are usually induced by problems in the manufacturing process. Therefore, defect pattern recognition is useful for root cause analysis, which is very important for yield optimization. Machine learning (ML) based methods can achieve good LDP recognition rate. In general, these techniques are designed to identify spatial patterns, which may not directly linked to the root cause. Besides, ML methods are more time-consuming because of the training process. In this paper, we propose to apply a rule-based method for LDP classification such that the recognized patterns are explainable. Experimental results show that the proposed method achieves roughly the same level of accuracy as other ML methods while the exaction time is much faster.

To achieve wafer testing with high precision, it is necessary to thoroughly clean the probing needles. Currently, the level of cleanliness is determined according to prior experience and the frequency of die failures. The current cleaning process is inefficient since there is no mechanism to identify embedded and bonded debris (foreign material) prior to the test, which may result in yield loss. In addition, over cleaning reduces a needle's life. To address this problem, we propose a framework based on real-time images and die contact resistance. The proposed framework employs image processing and supervised machine learning techniques to develop a recognition framework for detecting sudden foreign material buildups and monitoring needle degradation over time.

Paper-based digital microfluidic biochip (PB-DMFB) technology is one of the most promising solutions in biochemical applications due to the paper substrate. The paper substrate makes PB-DMFBs more portable, cost-effective, and less dependent on manufacturing equipment. However, the single-layer paper substrate, which entangles electrodes, conductive wires, and droplet routing in the same layer, raises challenges to chip-level synthesis of PB-DMFBs. Furthermore, current design automation tools have to address various design issues including manufacturing cost, reliability, and security. Therefore, a more flexible chip-level synthesis method is necessary. In this paper, we propose the first reinforcement learning based chip-level synthesis for PB-DMFBs. Double deep Q-learning networks are adapted for the agent to select and estimate actions, and then we obtain the optimized synthesis results. Experimental results show that the proposed method is not only effective and efficient for chip-level synthesis but also scalable to reliability and security-oriented schemes.

We propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

The scratch defect type is difficult to recognize because the position, shape, size and curvature vary widely from one scratch to another. Discontinuity points within scratches also contribute to the low recognition rate, and such points are often hidden defective dies that become reliability threat. The recognition rate for scratches is among the lowest in all patterns even if the overall accuracy is high. In this paper, we propose a novel scratch pattern recognition method. The method is validated by real products. Experimental results show that the average recall, precision and accuracy achieved by the proposed method are 97.22%, 98.81%, and 99.92%, respectively. Furthermore, the proposed method is based on image processing techniques alone with low processing time. In contrast to machine-learning based methods, there is no need to train a complicated prediction model.

Wafer map defect pattern recognition is valuable for root cause analysis and yield learning. Most of the previous studies on defect pattern recognition are based on supervised machine learning, in which labeled wafer maps are used to train a machine learning model for automatic classification. Some problems arise in this approach. First, there may be misclassification in the original labeled data, which makes it difficult to establish an accurate prediction model. Secondly, defect patterns that are not defined before will not be classified correctly. In this paper, we proposed a semi-supervised framework to deal with these problems. Labeled wafer maps are first used to train a prediction model, with likely misclassified data excluded. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns with enhanced labeling techniques. This proposed approach is validated with TSMC 811K database, in which we are able to define five new defect pattern types. Experimental results show that total 14 defect types can be recognized with overall accuracy of 94.37%.

Wafer map defect pattern recognition provides a visual way for root cause analysis and yield learning. Specially, recognizing grid, including line and intersection point types in wafer defect patterns is a challenging problem for process and test engineers. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects for yield ramp up. In this paper, we propose a grid pattern recognition methodology taking into account both partial and hidden grid patterns. Hidden defective dies are dies in the grid contour that pass wafer test. However, such dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the potential defective dies in hidden grid patterns and mark them as faulty. As a result, the reliability of products and test cost can be significantly improved. In this paper, we propose a systematic methodology to search for hidden grid patterns in wafers. A five-phase method is developed to enhance wafer maps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve 100% prediction accuracy for all grid types, and also achieve 96.45% by Extremely Randomized Trees for all nine common wafer defect types averagely.

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

Wafermap defect pattern detection and diagnosis provide useful clue to yield learning. However, most wafermaps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Specially, recognizing scratch and line types of defect patterns is a challenging problem for process and test engineers and it takes a lot of manpower to identify such patterns, as potential defective dies may exist on the scratch contour and become discontinuity points. However, such potential defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in potential scratch patterns and mark them as faulty. As a result, the quality and reliability of products can be significantly improved and cost of final test can be reduced. In this paper, we propose a systematic methodology to search for potential scratch/line defect types in wafers. A five-phase method is developed to enhance wafermaps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve more than 89% prediction accuracy for scratch/line types, and higher than 94% for all common wafer defect types.

Paper-based digital microfluidic biochip (PB-DMFB) technology provides a promising solution to many biochemical applications. However, PB-DMFB manufacturing process may suffer from potential security threats. For example, both Trojan insertion and man-in-the-middle attack may affect the functionality of PB-DMFBs. To ensure the correct functionality of PB-DMFBs, we propose a watermarking scheme to hides information in the PB-DMFB layout, which allows users to check design integrity and authenticate the source of the PB-DMFB design. As a result, it serves as a first countermeasure against both Trojan insertion and man-in-the-middle attacks for PB-DMFBs.

We propose a machine learning based method targeted for accurate wafer defect map classification. The proposed method is referred to as TestDNA-E, as it applies ensemble learning based on improved TestDNA features. Experimental results show that the proposed method achieves high hit rate for each defect type and overall accuracy.

Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

The Physical Unclonable Function (PUF) has been proposed for the identification and authentication of devices and cryptographic key generation. A strong PUF provides an extremely large number of device-specific challenge-response pairs (CRP) which can be used for identification. Unfortunately, the CRP mechanism is vulnerable to modeling attack, which uses machine learning (ML) algorithms to predict PUF responses with high accuracy. Many methods have been developed to strengthen strong PUFs with complicated hardware; however, recent studies show that they are still vulnerable by leveraging GPU-accelerated ML algorithms.

Wafer defect maps exhibit spatial failure pattern recognition for root cause analysis to improve defect diagnosis resolution and yield learning conventionally. We apply further product-driven test items to propose a wafer-level test methodology to generate a DNA-like wafer defect signature to identify wafer defects. Experience results show that our TestDNA are both effective and efficient, including the tight relation with traditional wafer defect patterns, high prediction accuracy over 90%, and improved lower non-pattern ratio from over 95% to around 11%.

Paper-based digital microfluidic biochips (PB-DMFBs) provide a promising solution for microfluidic bioassays. Due to the low-cost substrate material and low demand for complicated manufacturing equipment, PB-DMFBs can be fabricated without foundry. On the flip side, convenience of fabrication allows PB-DMFBs to be fabricated everywhere, which makes it is difficult to manage production and distribution of IP (bioassays). As a result, PB-DMFBs are vulnerable to security threats. IP and its creator, the biocoders, may suffer from infringement. To ensure IP protection, in this paper, we proposed the first Digital Rights Management (DRM) scheme to protect IPs of PB-DMFBs from security threats. A chip-level synthesis algorithm is also presented to realize not only complex biochemical operations but also the demand of DRM.

Physical Unclonable Functions (PUF) have been proposed to deal with issues in hardware security. A PUF relies on the intrinsic manufacturing process variations to generate the device-specific responses to challenges. One popular way to implement PUFs is to exploit the unknown power-up values in memory elements as the PUF responses. Since it is difficult to turn on and off memory blocks repeatedly, it may be necessary to store the responses of memory-based PUFs on-chip, which makes the system more vulnerable to malicious attacks. In this paper, we propose a PUF design based on registers. The proposed register PUF can generate responses repeatedly on-line such that there is no need to store the responses. Experimental results show that the proposed design achieves good reliability, randomness, and uniqueness.

Signals in a digital system are coordinated by one or multiple clocks. To ensure the correct system operations, ideally all clock signals derived from a clock source should be synchronized through a clock distribution network (CDN). Clock delay faults in a CDN may create clock skews, which will change the timing behavior of a circuit and produce invalid results. Unfortunately, it is very difficult to detect such faults directly due to the large number of clock sinks and the lack of observability on the clock signals, and this topic is rarely studied previously. In this paper, we present a systematic way to detect faulty timing behavior due to the clock delay in a CDN. For each clock skew under test, we need to find out the longest sensitizable path in the combinational logic that can be used to detect the corresponding clock skew. Such structural paths can be found through static timing analysis (STA) or statistical STA. Launch-on-capture (LOC) test patterns for the candidate paths are then generated and compacted. Experimental results show that most of clock skews can be detected with a limited number of test vectors.

A systematic design methodology is presented for custom Network-on-Chip (NoC) in three-dimensional integrated circuits (3D-ICs). In addition, fault tolerance is supported in the NoC if extra links are included in the NoC topology. In the proposed method, processors and the communication architecture are synthesized simultaneously in the 3D floorplanning process. 3D-IC technology enables ICs to be implemented in smaller size with higher performance; on the flip side, 3D-ICs suffer yield loss due to multiple dies in a 3D stack and lower manufacturing yield of through-silicon vias (TSVs). To alleviate this problem, a known-good-dies (KGD) test can be applied to ensure every die to be packaged into a 3D-IC is fault-free. However, faulty TSVs cannot be tested in the KGD test. In this article, the proposed method deals with the problem by providing fault tolerance in the NoC topology. The efficiency of the proposed method is evaluated using several benchmark circuits, and the experimental results show that the proposed method produces 3D NoCs with comparable performance than previous methods when fault-tolerant features are not realized. With fault tolerance in NoCs, higher yield can be achieved at the cost of performance penalty and elevated power level.

Paper-based microfluidic chips provide a novel way to carry out microfluidic analysis. Such chips achieve “lab-on-paper” instead of traditional “lab-on-chips”. The paper substrate is attractive because it is cost-effective, easy to use and disposable. The routing problem of paper-based digital microfluidic (PB-DMF) biochips is to realize bio-chemical operations on paper with inkjet printing techniques. We propose a routing scheme targeting multiple preprogrammed droplet paths such that both routability and wire-length are optimized in a paper layer. Compared with previous digital microfluidic (DMF), the proposed paper-based DMF needs only one integrated paper layer instead of two layers of control and signal layers in the traditional DMF. Experimental results on a set of paper chip applications show the effectiveness, efficiency and scalability of the proposed algorithm.

The scan-based design provides a structural way to deal with the testing problem in modern VLSI circuits. With the help of scan chains, sequential elements become both observable and controllable. On the flip side, the scan chain also becomes a back door for reverse-engineering attack. It has been proved that scan-based side-channel attack can glean secrete information in encryption circuits implemented with linear operations. Many methods have been proposed to improve the security of scan chains, and it is suggested that a non-linear layer can be included to resist the attack. In this paper, we demonstrate that the modified scan chains can be neutralized even though non-linear operations are employed in the protection mechanisms. The attack is achieved through analyzing the distribution of 0's and 1's in the output response under given input stimuli, from which one can conjecture the true scan chain structure. Experimental results show that the proposed method can be used to attack non-linear circuits equipped with flipped scan chains.

Recently paper-based microfluidic chips have been proposed to achieve microfluidic analysis for many applications. Such chips achieve "lab-on-paper" instead of traditional "lab-on-chips". The paper substrate is attractive because it is cost-effective, easy to use and disposable, fully compatible with most medical/biochemical applications, and offering liquid flow by capillary without being relied on external forces and equipment. Test methods for digital microfluidic (DMF) biochips have been studied for years; however, they are developed for traditional DMF chips and thus are not directly applicable to paper-based DMF (PB-DMF) chips. In PB-DMF chips, electrodes are control wires are printed on the same paper surface, while electrodes can be placed with custom structure. In this paper, we present test and diagnosis methods for faults in PB-DMF. A design-for-diagnosability scheme is proposed, and it is shown that single faults can be located and tolerated by providing alternative paths in PB-DMF chips. The feasibility of the proposed method is validated through experiments.

Pre-bond testing of silicon interposer is difficult due to the large number of nets to be tested and small number of test access ports. Recently, it was proposed to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers provides access to nets that are not normally accessible. Previous synthesis method for test interposer was based on constrained breadth-first search, which can be time-consuming. Besides, separate test interposers have to be provided for open and short fault testing. In this paper, we present a theoretical study on the topology of testable circuit structure for interconnect faults in silicon interposer. Based on the theoretical framework, a more efficient synthesis method is developed. Furthermore, a single test interposer can be used for both open and short fault detection, which leads to shorter test time and lower test cost.

Output selection is recently proposed for test response compaction. This scheme achieves zero aliasing, full X-tolerance, and high diagnosability, at the cost of inflated test set and non-trivial hardware overhead. The time/space penalty in test output compaction is mainly attributed to the loss of observability. In previous methods, it was in general assumed that erroneous responses are uniformly distributed among all scan chains, and the output compactors are designed accordingly. In this paper, we present three techniques to improve the performance of output selection based test response compaction. (1) The uneven distribution of erroneous test responses is exploited to optimize compactor design. (2) A test dynamic compaction algorithm is provided to deal with the test set inflation problem. (3) A low-cost test response compactor is presented. Experimental results indicate that the proposed techniques can achieve better compaction results with lower hardware overhead.

The impact of process variation has been more prominent in nano-technology, and it poses great challenge to timing analysis for digital VLSI. Traditionally, this problem is solved by using statistical static timing analysis (SSTA). However, static timing analysis may lead to an overly pessimistic estimation, as many critical paths are not true paths. In this paper, we present a fast SSTA method, in which critical path traversal is combined with false path analysis so that true critical paths can be quickly identified. Experimental results show that a significant portion of the longest paths are actually false, which implies SSTA without false path analysis usually overestimate critical path delays.

The paper presents a built-in self-testing (BIST) technique for leakage monitoring using a time-based bootstrapped sensor at near-threshold supply. In order to observe critical leakage behavior in near-threshold systems, the BIST circuit duplicates the leakage current and a leakage quantizer converts the sensed current into digital outputs. Moreover, a bootstrapped ring oscillator (BTRO) serves as an ultra low-voltage sensor to operate even in deep sub-threshold region. It suppresses most of the leakage current and has high energy efficiency to convert sensed leakage current to oscillation frequency. As a result, it monitors leakage current from the circuit under test (CUT) and quantizes the leakage to high resolution digital outputs. In addition, our design also can be used to monitor the process variation in the ultra low-voltage application. The design and test technique is simulated in 90 nm 1P9M SPRVT CMOS process. As compared to state-of-art works, the proposed sensor can operate even at 0.2 to 0.4V VDD in different corners. Besides, it achieves 11-bit resolution under 10us testing time.

This paper presents a novel scheme for silicon interposer testing. Testing interpose is difficult due to the large number of nets to be tested and small number of test access ports. Previous methods can only achieve limited fault coverage for open faults. We propose to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers will provide access to nets that are not normally accessible; thus, most or all nets become testable. Furthermore, both open and short faults in the interconnect structure can be tested. The efficiency of the proposed test scheme is mainly affected by the structure of test interposer; thus, algorithms for the generation of optimized test interposers are explored. Experimental results show that all faults can be efficiently tested with the proposed method.

Three-dimensional integrated circuits (3D-ICs) is a promising way to implement system-on-chip. To achieve acceptable manufacturing yield, pre-bond test is necessary to make sure only good dies are bonded. A true 3D clock tree requires shorter overall routing lengths and consumes lower power. However, a true 3D clock tree also renders pre-bond test impossible since there are not complete clock trees in dies under test. Therefore, redundant trees have to be added to make dies pre-bond testable. In this paper, we propose a heuristic approach for 3D clock tree synthesis targeted to minimize the number of Through-Silicon-Vias (TSV) and reduce the overhead for redundant trees. Experimental results show that the proposed method can achieve both goals efficiently.

We propose a full-chip synthesis methodology to construct custom network-on-chips (CusNoCs) for NoC-based systems. The proposed scheme generates irregular network topologies for application-specific designs with known communication demands. In this method, processors and the communication architecture can be synthesized simultaneously in the floorplanning process, and thus it is called CusNoC. CusNoC synthesizes CusNoC in two steps. The target network topology is first generated based on communication analysis. Processing elements are partitioned into groups such that the utility of routers will be maximized if a router is assigned to each group. In this way, the number of routers passed by a packet, or hops, is minimized, and so is the power consumption in the network. The final network topology is formed by properly connecting these groups. A wirelength-aware floor planning is then carried out to optimize circuit size as well as wirelength. Experimental results show that CusNoC produces custom NoCs with better performance than previous methods while the computation time is significantly shorter. This method is also more scalable, which makes it ideal for complicated systems.

In this brief, we propose an oscillation-ring test methodology for synchronous sequential circuits under the scan test environment. This approach provides the following features: 1) it is at-speed testing, which makes delay defects detectable; 2) the automatic test pattern generation is much easier, and the test set is usually smaller; and 3) test responses are directly observable at primary outputs and, thus, it greatly reduces the communication bandwidth between the automatic test equipment and the circuit under test. A modified scan register design supporting the oscillation-ring test is presented and an effective oscillation test generation algorithm for the proposed test scheme is given. Experimental results on LGSyn91 benchmarks show that the proposed test method achieves high fault coverage with a smaller number of test vectors.

On-chip interconnect structures become much more complicated and dominate system performance in multicore system-on-chips. Oscillation ring (OR) test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that both 100% fault coverage and the optimum diagnosis resolution for various fault models are achievable. The cost of OR test is decided by the number of test sessions required to form all the rings. Previous ring generation algorithm tries to generate long rings that usually cannot be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this brief, we study techniques to generate rings that can be tested concurrently, so that the overall test time can be reduced significantly.

Three-dimensional integrated circuits (3D-ICs) create new test challenges. Because of the limited number of test pads available in pre-bond test, the IR-drop can become a serious problem in delay test. In this paper we present a low-power delay test architecture, in which scan flip-flops are partitioned into groups that can be selected turned off in the capture cycles. As a result, power consumption in the capture cycles can be reduced significantly and thus IR-drop can be alleviated. Experimental results show that the proposed method can achieve the same level of delay fault coverage with roughly the same number of test vectors, while capture cycle power consumption is lower.

An interconnect-driven layout-aware multiple scan tree (MST) synthesis methodology for 3-D integrated circuits (ICs) is proposed. MSTs, also known as scan forest, greatly reduce test data volume and test application time in system-on-a-chip testing. Previous studies on layout-aware scan tree synthesis only address 2-D layouts, so they cannot be directly applied to 3-D ICs. The proposed algorithm effectively optimizes both test compression rate and routing length under 3-D IC-induced constraints, and produces better results than all previous known methods.

This paper proposed a full-chip testing scheme for 3D ICs to achieve the integrated horizontal/vertical interconnect reliability and yield enhancement with targets of interconnect faults under stuck-at and open fault models. This scheme is based on our previously developed IEEE std. 1500 compatible oscillation-ring (OR) testing methodology and further applies to Through-Silicon-Vias (TSVs)-based 3D ICs. The experimental results show that the both horizontal and vertical ring generation algorithms can achieve the optimal detectability for any interconnect. Compared with our previous work (IORT) in 2D ICs, the proposed HVOR needs only 43% extra rings for achieving 100% fault coverage in a 2-tier 3D ICs, and this work needs 82% testing time due to the concurrency characteristic in OR test scheme.

This paper proposes a resilient scheme to achieve maximal interconnect fault tolerance, reliability and yield for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this scheme can tolerate faulty connections by efficiently finding alternative paths with modified Longest Common Subsequence. This scheme is compatible with previous interconnect detection and diagnosis methods, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple faults. Furthermore, this scheme can identify connections which will cause communication failure if they are faulty. With this knowledge, designers can significantly improve interconnect reliability by augmenting such vulnerable connections. Experimental results show that alternative paths can be found for almost all paths in this scheme, this it provides a way to achieve fault-tolerant and reliability/yield improvement.

A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time, and test data compression rate simultaneously is proposed in this paper. Multiple scan trees, also known as a scan forest, greatly reduce test data volume and test application time in system-on-chip testing. However, previous research on scan tree synthesis rarely considered issues such as, routing length and output port limitation, and hence created scan trees with a large number of scan output ports and excessively long routing paths. The proposed algorithm provides a mechanism that effectively reduces test time and test data volume, and routing length under output port constraint. As a result, very few or no output compressors are required, which significantly reduces the hardware overhead.

A novel oscillation-based on-chip thermal sensing architecture for dynamically adjusting supply voltage and clock frequency in system-on-chip (SoC) is proposed. It is shown that the oscillation frequency of a ring oscillator reduces linearly as the temperature rises, and thus provides a good on-chip temperature sensing mechanism. An efficient dynamic frequency-to-voltage scaling (DF2VS) algorithm is proposed to dynamically adjust supply voltage according to the oscillation frequencies of the ring oscillators distributed in SoC so that thermal sensing can be carried at all potential hot spots. An on-chip Dynamic Voltage Scaling or Dynamic Voltage and Frequency Scaling (DVS or DVFS) monitor selects the supply voltage level and clock frequency according to the outputs of all thermal sensors. Experimental results on SoC benchmark circuits show the effectiveness of the algorithm that a 10% reduction in supply voltage alone can achieve about 20% power reduction (DVS scheme), and nearly 50% reduction in power is achievable if the clock frequency is also scaled down (DVFS scheme). The chip temperature is reduced accordingly.

A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time and test data compression rate simultaneously is proposed in this paper. Multiple scan trees, also known as a scan forest, greatly reduce test data volume and test application time in SoC testing. However, previous research on scan tree synthesis rarely considered issues such as routing length and output port limitation, and hence created scan trees with a large number of scan output ports and excessively long routing paths. The proposed algorithm provides a mechanism that effectively reduces test time and test data volume, and routing length under output port constraint. As a result, no output compressors are required, which significantly reduce the hardware overhead.

On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the number of test sessions required to form all the rings. Previous method on ring generation algorithm uses depth-first-search (DFS) based method to generate long rings that may pass more uncovered edges. However, very few of the long rings can be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this paper, we present several techniques to generate rings that can be tested concurrently. (1) Two ring generation algorithms are proposed to generate shorter rings that can be applied in parallel to reduce overall test time. (2) Multilevel framework is applied to optimize parallelism. Experimental results show that the proposed ring generation algorithms improve test application time by 2.25X, and with multilevel framework the improvement is 4.13X. All the ring generation algorithms achieve 100% interconnect fault coverage.

Power consumption is an important issue in nanoscale circuits. The multiple supply voltages (MSV) technique, where non-critical parts are supplied with the lower supply voltage, can be used to balance power and performance, as both dynamic and leakage power are reduced with the lower supply voltage. However, level converting circuits must be inserted between different voltage domains to avoid leakage current. In this paper, we present three scan flip-flop designs that support a low-power mechanism, including level converting and sleep mode operation. The designs provide tradeoff between power and speed, and thus provide a simple and efficient way to design low-power high-testability circuits.

The n-detection test is attractive as it achieves high defect coverage for all types of circuits and different fault models by using an easy ATPG procedure. The drawback is that it requires a much larger test set; besides, the test power is also a concern. Since the size of an n-detection test set is very large, it is possible to organize the test patterns in such a way that signal transitions are distributed more evenly among all patterns; thus, a lower peak capture power can be achieved. The reduction in peak power is very desirable, as it reduces the risk of invalid test due to IR-drop and chip overheating. In this paper, we present a low capture power ATPG and a power-aware test compaction method. Two goals are achieved by the proposed ATPG. (1) The growth of test pattern count is lower than the detection number n. (2) The peak power becomes smaller as the detection number n increases. The test compaction algorithm further reduces the number of test patterns as well as the average capture power. The efficiency of the proposed method is illustrated through experiments with some ISCAS'89 benchmark circuits. Experimental results show that the aforementioned two goals are achieved; furthermore, the average power consumption is also improved when n becomes larger.

The degree of achievable test-data compression depends on not only the compression scheme but also the structure of the applied test data. Therefore, it is possible to improve the compression rate of a given test set by carefully organizing the way that test data are present in the scan structure. The relationship between signal probability and test-data entropy is explored in this paper, and the results show that the theoretical maximum compression can be increased through a partition of scan flip-flops such that the test data present in each partition have a skewed signal distribution. In essence, this approach simply puts similar scan flip-flops in an adjacent part of a scan chain, which also helps to reduce shift power in the scan test process. Furthermore, it is shown that the intrapartition scan-chain order has little impact on the compressibility of a test set; thus, it is easy to achieve higher test compression with low routing overhead. Experimental results show that the proposed partition method can raise the compression rates of various compression schemes by more than 17%, and the average reduction in shift power is about 50%. In contrast, the increase in routing length is limited.

For very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.

An interconnect-driven layout-aware multiple scan tree synthesis methodology is proposed in this paper. Multiple scan trees greatly reduce test data volume and test application time. However, previous researches on scan tree synthesis rarely considered routing length issues, and hence create scan trees with long routing paths. The proposed algorithm effectively considers both test compression rate and routing length and hence produces better results than all previous known methods in both regards. In this method, a density-driven dynamic clustering algorithm is applied to determine scan cells in each scan tree. A compatibility based clique partition algorithm is used to determine tree topology, and then a Voronoi diagram is used to establish physical connections. Compared with the previous results on scan tree synthesis, the proposed method achieves better compression rate with smaller routing overhead.

Code-based test data compression schemes encode symbols in the test data with predetermined codewords so that data volume can be reduced. The compression efficiency is affected by the distribution of data symbols. In this paper, we first analyze the factors that affect the encoding efficiency in various codes, and then propose a skewed-distribution scan chain partitioning scheme, in which the distribution of 0’s and 1’s are changed in different parts of the scan chain. Both analytical and experimental results confirm that the scheme can effectively improve compression efficiency, while the routing penalty due to the partitioning method is limited.

Launch-off-shift (LOS) is a popular delay test technique for scan-based designs. However, it is usually not possible to achieve good delay fault coverage in LOS test due to conflicts in test vectors. In this article, we propose a layout-based scan chain ordering method to improve fault coverage for LOS test with limited routing overhead. A fast and effective algorithm is used to eliminate conflicts in test vectors while at the same time restrict the extra scan chain routing. This approach provides many advantages. (1) The proposed method can improve delay fault coverage for LOS test. (2) With layout information taken into account, the routing penalty is limited, and thus the impact on circuit performance will not be significant. Experimental results show that the proposed LOS test method achieves about the same level of delay fault coverage as enhanced scan does, while the average scan chain wire length is about 2.2 times of the shortest scan chain.

In this paper, we propose a layout-aware scan tree synthesis methodology. Scan tree can greatly reduce test data volume, which is very desirable in SOC testing. However, previous researches on scan tree synthesis have not considered routing issues in physical design, which may create a tree with excessively long routing path. In this paper we present a multi-layer multi-level scan tree synthesis method, in which both data compression and routing length are taken into account. Experimental results show that the proposed test method achieves high compression rate with limited routing overhead.

Launch-off-Shift (LOS) is a widely used technique for delay test in scan-based design. Test data compression for LOS patterns, however, is less efficient. In this paper, we first analyze the reason for low compression rate in LOS patterns, and present an LOS test enabled scan architecture that supports three operation modes: broadcast, multicast, and serial. Efficient LOS test data compression can be achieved under this architecture with limited hardware overhead. An ATPG method for LOS test patterns under the proposed architecture is also presented. Experimental results show that most of the serial scan operations can be replaced by multicast operations, and thus achieve much better compression rate.

In this paper, we propose an automatic test pattern generation (ATPG) scheme for low power launch-off-capture (LOC) transition test. Two techniques are explored in the proposed ATPG. A bidirectional X-filling, in which both line justification and logic simulation are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. For vectors producing very large capture power, a test vector replacement scheme is applied to efficiently reduce the peak capture power. The proposed method does not change the test architecture, and thus no hardware overhead is required. Experimental results show that the proposed scheme outperforms previous method by 50% in both peak power and average capture power.

We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. 2) We present a heuristic to reduce routing congestion to optimize the multiple-fault probability, chemical-mechanical polishing- and optical proximity correction-induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the Microelectronics Center for North Carolina benchmark circuits show that the proposed ORT method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects. Further, the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion.

We propose an interconnect diagnosis scheme based on oscillation ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and crosstalk glitches. We analyze the diagnosability of an interconnect structure and propose a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm which achieves the optimal diagnosability. Two optimization techniques improve the efficiency and effectiveness of interconnect diagnosis. In all experiments, our method achieves 100% fault coverage and the optimal diagnosis resolution.

In this paper, we propose a layout-based scan chain ordering method to improve fault coverage for skewed-load delay test with minimum routing overhead. This approach provides many advantages over previous methods. (1) The proposed method can provide 100% test pair coverage for all detectable transition faults. (2) With layout information taken into account, the routing penalty is small, and thus the impact on circuit performance is not significant

An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution

We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.

In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.

The crosstalk fault effects in deep sub-micron VLSI, namely, glitches and the crosstalk-induced delay, are investigated. The origin of their occurrence, relationship and importance in circuit operation are elucidated. It is shown that the crosstalk-induced delay is only superposition of the induced glitch with the original signal delay on the affected victim line; and crosstalk-induced delay is more important in affecting the circuit performance, and should be considered in more details for testing. A scheme which is to detect both types of faults in a unified way by just detecting glitches is proposed and studied, considering the manufacture process variation. In this way, detection of crosstalk-induced faults becomes much easier.

Crosstalk-induced noise has become a key problem in interconnect optimization when technology improves, spacing diminishes, and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this paper we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Experimental results show that our approach achieves an average success rate of 80.9% (78.2%) of nets meeting timing constraints alone (both timing and noise constraints) and consumes an average extra area of only 0.49% (0.66%) over the given floorplan, compared with the average success rate of 75.6% of nets meeting timing constraints alone and an extra area of 1.33% by the BBP method [3].