Global control signals account for over 10% of the circuit area and are challenging to diagnose when defects occur. This paper introduces a global signal diagnosis technique that can be easily integrated into the existing chain failure diagnosis flow in volume diagnosis. In addition to clock and scan enable signals, set and reset signals are also taken into account during diagnosis. The layout topology of global nets is utilized to improve the accuracy and resolution of the diagnosis result. The effectiveness of this method is validated through several physical failure analysis results.

Volume diagnosis is an essential step in diagnosis driven yield analysis. Generally, diagnosis run time increases when more failing patterns are collected in a fail log. In order to improve diagnosis throughput, pattern sampling, which only uses a subset of the failing patterns, is a common practice in volume diagnosis. Compared to the results achieved by using all the failing patterns, traditional pattern sampling has a negative effect on the diagnosis accuracy and resolution. In this paper, we propose a layout-aware active pattern sampling method which improves the quality of diagnosis in terms of accuracy and resolution over the traditional pattern sampling method. Meanwhile, it achieves higher diagnosis throughput compared with the non-sampling methodology. Diagnostic results on four industrial designs show that the average suspects per symptom are reduced by 10.77% ~35.86 % compared to the traditional pattern sampling method. Besides, our algorithm has an advantage of identifying more actual defective locations compared with the traditional sampling or non-sampling method.

Fault simulation plays an important role in ATPG and fault diagnosis of integrated circuits. However, with the increasing complexity of chips, the simulation of tens of millions faults of VLSI needs a lot of time and computing resources. To improve the simulation efficiency, many methods and technologies have emerged, such as GPU acceleration and distributed computing. However, there are some challenges and limitations to these approaches, such as high cost, high energy consumption, and programming complexity. In contrast, the acceleration of fault simulation based on ARM multi-core CPU has the characteristics of strong multi-threaded parallel computing capability, low cost, low energy consumption, and easy implementation. Therefore, a new method for accelerating fault simulation based on ARM multi-core CPU is proposed in this paper, which adopts an enhanced parallel simulation method. In this method, each node has its own memory space and processor, and the CPU can work at full load. This paper also provides solutions to NUMA affinity, cross-node access and other problems. This paper will elaborate on these methods and demonstrate their effectiveness and accuracy in fault simulation.