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Katsuhiko Seo

dblp:20/6312 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA-based genetic algorithm		 0.012000
An FPGA-based genetic algorithm machine (poster abstract) · FPGA 2000
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA coprocessor		 0.012000
An FPGA-based genetic algorithm machine (poster abstract) · FPGA 2000

Methods — techniques the papers use, named apart from their topics

genetic algorithm · 0.0
YearPublicationVenuePosition
2000 An FPGA-based genetic algorithm machine (poster abstract)
abstract
No abstract available.
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
 FPGA5
1998 A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture
abstract
We propose a top-down hardware/software co-simulation method for embedded systems and introduce a component logical bus architecture as an interface between software components and hardware components. Co-simulation using a component logical bus architecture is possible in the same environment from the stage at which the processor is not yet determined to the stage at which the processor is modeled in register transfer language. A model whose design is based on a component logical bus architecture is replaceable and reusable. By combining such replaceable models, it is possible to quickly realize seamless co-simulation. We further describe experimental results of our approach.
Mitsuhiro Yasuda, Katsuhiko Seo, Hisao Koizumi, Barry Shackleford, Fumio Suzuki
 ASP-DAC2
1997 A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
 ICONIP (1)5