EDBT 2026 Demo / reviewers in the wild / expert
Gerard A. Allan
dblp:20/6393
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 98% Integrated circuit design · 2% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.1 | 3 | 2000 | Yield prediction by sampling IC layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 Efficient extra material critical area algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 A yield improvement technique for IC layout using local design rules · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Electronic design automation › yield analysis
yield prediction |
0.1 | 2 | 2000 | Yield prediction by sampling IC layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 Efficient extra material critical area algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation › design for manufacturability
critical area extraction |
0.0 | 1 | 1999 | Efficient extra material critical area algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation › design for manufacturability › design for yield
yield enhancement |
0.0 | 1 | 1992 | A yield improvement technique for IC layout using local design rules · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Electronic design automation › physical design
layout analysis |
0.0 | 1 | 2000 | Yield prediction by sampling IC layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation
defect analysis |
0.0 | 1 | 1999 | Efficient extra material critical area algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation › physical design › VLSI layout
mask layout |
0.0 | 1 | 1999 | Efficient extra material critical area algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Integrated circuit design › VLSI design
IC layout |
0.0 | 1 | 1992 | A yield improvement technique for IC layout using local design rules · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Methods — techniques the papers use, named apart from their topics
survey sampling · 0.0monte carlo sampling · 0.0edge-based critical area algorithm · 0.0track width adjustment · 0.0track displacement · 0.0contact size adjustment · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Yield prediction by sampling IC layoutabstractThis paper reports a survey sampling-based methodology for critical area and other property estimates of IC layout. A software implementation of the method, Edinburgh yield estimator sampling (EYES) is presented. The EYES tool implements the survey sampling-based methodology for critical area estimation enabling the yield prediction of ULSI chips. The method requires an analysis of only a small fraction of the chip layout. As a result the practical application of the technique is not limited by the size of the chip, or the design hierarchy. The EYES system is able to process non-Manhattan layout. This enables yield predictions in a reasonable time for even the largest state-of-the-art chips, using modest computing resources. Gerard A. Allan |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1999 | Efficient extra material critical area algorithmsabstractTwo algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a given size. The edges are used to generate fault critical areas which are classified by the list of circuit nodes that are shorted by a defect of a given size falling within that area. These algorithms can be used as a framework on which other critical area algorithms can be generated, notably missing material and pinhole critical generation. The algorithms presented in this paper have the advantage that they are not restricted to Manhattan layout and that they are computationally efficient. Gerard A. Allan, Anthony J. Walton |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1992 | A yield improvement technique for IC layout using local design rulesabstractThe concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples.> Gerard A. Allan, Anthony J. Walton, Robert J. Holwill |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |