Digital harmonic-cancelling sine-wave synthesizers (DHSSs) enable programmable, low cost, spectrally pure, sinusoidal signal synthesis for application areas such as communication systems, and on-chip testing of analog/mixed-signal integrated circuits. The implementation of a DHSS requires a digital-to-analog converter (DAC). However, unlike a conventional binary-coded DAC, the harmonic-cancelling DAC (HC-DAC) used in a DHSS scales the input digital signals by a set of irrational amplitude weights. Consequently, the conventional knowledge of how amplitude resolution affects a binary-coded DAC does not apply to HC-DACs. In this paper, we present a mathematical study of how amplitude resolution and unit-element mismatch affects the signal-to-distortion (SDR) ratio of an HC-DAC. The results of the study show that it is possible to find a Pareto optimal value of amplitude resolution for a given HC-DAC with a target SDR. The values of SDR estimated from the mathematical model have been verified against circuit simulation results from two HC-DAC designs created using a 013 μm CMOS technology.

An on-chip sine-wave synthesizer design with fast programmability and low hardware cost is presented. The design makes use of a harmonic cancellation technique to digitally synthesize an approximation to a sine-wave, which does not contain lower order harmonic distortions. The remaining higher order harmonics are attenuated with the use of a low pass filter (LPF) to synthesize a spectrally pure sine-wave. The simple nature of the sine-wave synthesis approach allows for a design with low hardware cost while maintaining high output spectral purity. The generic design of the aptly named digital harmonic-cancelling sine-wave synthesizer (DHSS) is discussed along with parasitic extracted simulation results from a prototype designed in a 0.13 μm CMOS process. Simulation results demonstrate that the DHSS prototype is capable of synthesizing up to 100 MHz output frequency, with 43.5 dB SFDR, while consuming only 2.26 mW of power.

Sine-wave synthesizers are a core requirement in many electronic applications, such as communication systems, and test and verification of analog/mixed-signal electronic systems. In sine-wave synthesizers, there exists a compromise between output spectral purity and hardware complexity. Harmonic-cancelling sine-wave synthesizers (HCSSs) allow spectrally pure signal synthesis at low hardware cost, compared to conventional sine-wave synthesis approaches. In this paper, we propose a digital HCSS hardware architecture, which is simpler, more hardware efficient and more programmable compared to state of the art HCSSs. The proposed architecture has been verified through a prototype built from an FPGA and discrete components. Prototype results demonstrate 51.9 dBc spurious free dynamic range (SFDR) and an output frequency range from 100 Hz to 100 kHz.

The paper presents a performance analysis of direct sequence ultra wideband (DS-UWB) systems operating with non-linear receiver front-ends. Following this analysis, we propose the novel use of pulse doublets to mitigate non-linearity induced distortion. The signal-to-noise-and-distortion ratio (SNDR) and bit error rate (BER) are evaluated with varying degrees of non-linearity and interference power. Simulation results indicate significant performance improvements by using pulse doublets under high interference power and non-linear operating conditions. Using pulse doublets allows reduced front-end linearity requirements and enables improvements in more critical circuit parameters. Front-end modules, such as low noise amplifiers (LNAs), mixers and baseband amplifiers, are designed using Peregrine's 0.5 /spl mu/m SOS-CMOS process to demonstrate the benefits of circuits designed with relaxed linearity requirements. Simulation results obtained using the Cadence Spectre RF simulator indicate that the sub-linear front-end achieves 33 dB increase in voltage gain, 2 dB improvement in noise figure, 64% saving in power and 917 MHz extension in bandwidth over its more linear counterpart.

This paper presents an overview of the physical layer (PHY) and medium access control layer (MAC) requirements for a new class of high-speed wireless local area networks (WLANs) operating in the 5 GHz Unlicensed National Information Infrastructure (UNII) bands at data rates of 6-54 Mbps.

Analytic limitations on the noise transfer function of sigma-delta modulators are derived. The noise transfer function magnitude in decibels integrated against frequency sums to at least zero. An excess delay of one sample in the modulator feedback loop is found to be detrimental for lowpass modulators.

This paper presents the architecture, design and implementation of a 16 point FFT processor for a high speed wireless local area network. The 110000-transistor chip is implemented in 0.6 /spl mu/m TLM CMOS, operates worst case at 50 MHz at a supply voltage of 2.5 volts, and consumes 80 mW.

This paper summarizes aspects of the VLSI development of a high-speed wireless local area network (WLAN). The implications for system-on-a-chip designs are summarized.

We have implemented the digital section of a wireless local area network (WLAN) demodulator in a reconfigurable interface card called the PCI Pamette. The entire baseband section of the demodulator has been implemented using the Pamette and a simple analog to digital mezzanine board. This is the second version of the demodulator, the first being a card-based design using a mixture of discrete and reconfigurable logic. The Pamette design took far less time to complete than the card-based one. Moreover, the reconfigurable substrate is much more versatile. We describe the Pamette implementation and discuss our experiences with the two different design styles and technologies.

This paper summarizes some of the problems facing designers of leading edge CMOS ICs in the 1990s. The author examines the current state of VLSI electronic design automation relating to the design of large, high speed or low power, digital CMOS chips. He provides some pointers to future directions for CAD research and possible ways of approaching these problems in the business and academic environments of today.>

Dynamic time warping is a well-established technique for time alignment and comparison of speech and image patterns. This paper decribes the architecture, algorithms, and design of a CMOS integrated processing array used for computing the dynamic time warp algorithm. Emphasis is placed on speech recognition applications because of the real-time constraints imposed by isolated and continuous speech recognition.

Dynamic time warping is an established technique for time alignment and comparison of speech segments in speech recognition. This paper describes a CMOS integrated array processor for computing the dynamic time warp algorithm. It allows many popular variations including LPC and frequency domain representations of speech. High speed is obtained by extensive pipelining, parallel computation, and simultaneous matching of multiple patterns. A realistic application using 40 nine-component LPC vectors per word permits 10,000 word comparisons per second or, equivalently, real time recognition of a 10,000 word vocabulary.

Contour (polygon) filling is a primitive required in many application areas of raster scan graphics. The bit-map memory in a frame-store display is computationally well suited to this task, as it provides a large scratch pad working space. In this paper, a number of contour filling algorithms based on the read/write properties of the frame-store memory are compared with the classical `ordered-edge-list' approach. Performance is evaluated on a microcomputer controlled frame-store display system in terms of ability to fill correctly, execution speed and processor memory requirements. A new algorithm, based on a more exact definition of an object edge, is presented. This algorithm, denoted edge flag algorithm, is implemented within the frame-store memory. It features high speed, in conjunction with minimal CPU memory requirements, making it ideally suited to hardware or microcode (firmware) implementation.

Raster-scan color graphic displays provide increased visual feedback in many CAD areas. In addition the unique architecture of displays used for this purpose enable other CAD related problems to be solved within the hardware structure of the display. Achieving these features commensurate with human response times requires new architecures and algorithm development for color displays.

A frame store display station capable of generating real time animation effects using filled polygonal shapes is described. The system consists of a host microcomputer, a high performance frame store display controller and a microprogrammed graphic command interpreter. Real time performance is attained using a combination of software, hardware and a systems approach. The display station can be used to interactively test and view simple animation sequences. Some proposals for further increasing performance are discussed.