A new scheme for precisely scaling numbers in the residue number system (RNS) is presented. The scale factorKcan be any number coprime to the RNS moduli. Lookup table implementations are used as a basis for comparisons between the new scheme and scaling schemes from the literature. It is shown that new scheme decreases hardware complexity compared to previous schemes without affecting time complexity.

Thirty-four undergraduates implemented a MIPS R2000 processor for an introductory CMOS VLSI design course. This included designing a microarchitecture in Verilog, developing custom PLA generation and ad-hoc random testing tools, creating a standard cell library, schematics, layout, and PCB test board. The processor was fabricated by MOSIS on an AMI 0.5-micron process, included 160,000 transistors, and ran at 7.25 MHz.

A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the quotient digit's magnitude is calculated by comparing the truncated partial remainder with two limited precision multiples of the divisor. The sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using logical synthesis shows a latency of 2.34 ns for the recurrence of the proposed divider. It is ∼22% less than the conventional implementation.

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney [46], J. E. Robertson [47], and T. D. Tocher [48]. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature.

We consider the problem of recoding a number to minimize the number of nonzero digits in its representation, that is, to minimize the weight of the representation. A general sliding window scheme is described that extends minimal binary sliding window conversion to arbitrary radix and to encompass signed digit sets. This new conversion expresses a number of known recoding techniques as special cases. Proof that this scheme achieves minimal weight for a given digit set is provided and results concerning the theoretical average and worst-case weight are derived.

This paper considers the combination of two familiar, but hitherto incompatible, arithmetic techniques: optimised squaring and precomputing partial products. Optimised squaring reduces the total accumulation effort required for squaring when compared with multiplication, by removing repeated digit products from the accumulation tree. Iterative implementations of integer multiplication, in which each partial product is evaluated and accumulated in turn, can often be accelerated by precomputing the set of partial products and accumulating these as required. Iterative implementations of optimised squaring cannot benefit from the same straightforward technique. A new algorithm for optimised squaring is developed which reconciles the these two techniques and which is an improvement over squaring by multiplication for some platforms. The result is of significance for the implementation of public key cryptography on smart cards or other small footprint devices.